Datasheet

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AVAILABLE OPTIONS
ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
(1)
TPS2376-H
SLVS646A – SEPTEMBER 2006 – REVISED SEPTEMBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
UVLO THRESHOLDS (NOMINAL) PACKAGE
(1)
T
A
MARKING
TYPE LOW HIGH SO-8 PowerPad
-40 ° C to 85 ° C Adjustable 1.93 V 2.49 V TPS2376DDA-H 2376-H
(1) Add an R suffix to the device type for tape and reel.
over operating free-air temperature range (unless otherwise noted)
(1)
, voltages are referenced to V
(VSS)
TPS2376-H
VDD, RTN
(2)
, DET, PG -0.3 V to 100 V
Voltage ILIM, UVLO -0.3 V to 10 V
CLASS -0.3 V to 12 V
RTN
(3)
Internally Limited
Current, sinking PG 0 to 5 mA
DET 0 to 1 mA
CLASS 0 to 50 mA
Current, sourcing
ILIM 0 to 1 mA
Human body model 2 kV
ESD
System level (contact/air) at RJ-45
(4)
8/15 kV
T
J
Maximum junction temperature range Internally limited
T
stg
Storage temperature range -65 ° C to 150 ° C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 ° C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) I
(RTN)
= 0
(3) SOA limited to V
(RTN)
= 80 V and I
(RTN)
= 900 mA.
(4) Surges applied to RJ-45 of Figure 1 between pins of RJ-45, and between pins and output voltage rails per EN61000-4-2, 1999.
θ
JA
θ
JA
θ
JA
(Best)
PACKAGE
(2)
(Modified HIGH-K) (Modified LOW-K)
° C/W
° C/W ° C/W
DDA 58.6 50 45
(1) Tested per JEDEC JESD51, natural convection. The definitions of high-k and low-k are per JESD 51-7
and JESD 51-3. Modified low-k (2 signal - no plane, 3 in. by 3 in. board, 0.062 in. thick, 1 oz. copper)
test board with the pad soldered, and an additional 0.12 in.
2
of top-side copper added to the pad.
Modified high-k is a (2 signal – 2 plane) test board with the pad soldered. The best case thermal
resistance is obtained using the recommendations per SLMA002 (2 signal - 2 plane with the pad
connected to the plane).
(2) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI Web site at www.ti.com .
2
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