Datasheet

Inrush
V -V
APb RTN
I
PI
V -V
VC RTN
V
OUT
V -V
VDD RTN
PIPowered
SwitchingStarts
50V/div
2V/div
10V/div
100mA/div
10V/div
t-Time-10ms/div
TPS23757
SLVS948D –JULY 2009–REVISED NOVEMBER 2013 www.ti.com
Inrush and Startup
The TPS23757 provides a 140 mA inrush limit that is compatible with both type 1 and type 2 PSEs. The
TPS23757’s internal softstart permits control of the converter startup preventing the converter from exceeding the
PSE output limitations. APb becomes valid within t
APb
after converter switching starts, or if an adapter is plugged
in while the PD is operating from a PSE.
Maintain Power Signature
The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating
voltage is applied. A valid MPS consists of a minimum dc current of 10 mA (or a 10 mA pulsed current for at
least 75 ms every 325 ms) and an ac impedance lower than 26.3 kΩ in parallel with 0.05 μF. The ac impedance
is usually accomplished by the minimum operating C
IN
requirement of 5 μF. When either APD or DEN is used to
force the hotswap switch off, the dc MPS will not be met. A PSE that monitors the dc MPS will remove power
from the PD when this occurs. A PSE that monitors only the ac MPS may remove power from the PD.
Startup and Converter Operation
The internal PoE UVLO (Under Voltage Lock Out) circuit holds the hotswap switch off before the PSE provides
full voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and
classification. The converter circuits will discharge C
IN
, C
VC
, and C
VB
while the PD is unpowered. Thus V
VDD
-V
RTN
will be a small voltage just after full voltage is applied to the PD, as seen in Figure 20. The PSE drives the PI
voltage to the operating range once it has decided to power up the PD. When V
VDD
rises above the UVLO turn-
on threshold (V
UVLO-R
, ~35 V) with RTN high, the TPS23757 enables the hotswap MOSFET with a ~140 mA
(inrush) current limit as seen in Figure 21. Converter switching is disabled while C
IN
charges and V
RTN
falls from
V
VDD
to nearly V
VSS
, however the converter startup circuit is allowed to charge C
VC
(the bootstrap startup
capacitor). Additional loading applied between V
VDD
and V
RTN
during the inrush state may prevent successful PD
and subsequent converter start up. Converter switching is allowed if the PD is not in inrush, converter OTSD
(over-temperature shutdown) is not active, and the V
C
UVLO permits it. Once the inrush current falls about 10%
below the inrush current limit, the PD current limit switches to the operational level (~450 mA). Continuing the
startup sequence shown in Figure 21, V
VC
continues to rise until the startup threshold (V
CUV
, ~9 V) is exceeded,
turning the startup source off and enabling switching. The V
B
regulator is always active, powering the internal
converter circuits as V
VC
rises. There is a slight delay between the removal of charge current and the start of
switching as the softstart ramp sweeps above the V
ZDC
threshold. V
VC
falls as it powers both the internal circuits
and the switching MOSFET gates. If the converter control bias output rises to support V
VC
before it falls to V
CUV
–
V
CUVH
( ~5.5 V), a successful startup occurs. APb in Figure 21 becomes active within t
APb
from the start of
switching, indicating that an adapter is plugged in.
Figure 21. Power Up and Start
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