Datasheet

EVM Assembly Drawings and Layout Guidelines

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The DC/DC converter layout can benefit from basic rules such as:

• Pair signals to reduce emissions and noise, especially the paths that carry high-current pulses which

include the power semiconductors and magnetics.

• Minimize trace length of high-current, power semiconductors and magnetic components.

• Where possible, use vertical pairing.

• Use the ground plane for the switching currents carefully.

• Keep the high-current and high-voltage switching away from low-level sensing circuits including those

outside the power supply.

• Pay special attention to spacing around the high-voltage sections of the converter.

7.3 EMI Containment

• Use compact loops for dv/dt and di/dt circuit paths (power loops and gate drives).

• Use minimal, yet thermally adequate, copper areas for heat sinking of components tied to switching

nodes (minimize exposed radiating surface).

• Use copper ground planes (possible stitching) and top layer copper floods (surround circuitry with

ground floods).

• Use four-layer PCB if economically feasible (for better grounding).

• Minimize the amount of copper area associated with input traces (to minimize radiated pickup).

• Hide copper associated with switching nodes under shielded magnetics where possible.

• Heat sink the “quiet side” of components instead of the “switching side” where possible (like the output

side of inductor).

• Use Bob Smith terminations, Bob Smith EFT capacitor, and Bob Smith plane.

• Use Bob Smith plane as ground shield on input side of PCB (creating a phantom or literal earth

ground).

• Use LC filter at DC/DC input.

• Dampen high-frequency ringing on all switching nodes if present (allow for possible snubbers).

• Control rise times with gate drive resistors and possibly snubbers.

• Switching frequency considerations

• Use of EMI bridge capacitor across isolation boundary (isolated topologies)

• Observe the polarity dot on inductors (embed noisy end).

• Use of ferrite beads on input (allow for possible use of beads or 0-Ω resistors)

• Maintain physical separation between input-related circuitry and power circuitry (use ferrite beads as

boundary line).

• Balance efficiency vs acceptable noise margin

• Possible use of common-mode inductors

• Possible use of integrated RJ-45 jacks (shielded with internal transformer and Bob Smith terminations)

• End-product enclosure considerations (shielding)

TPS23756EVM SLVU329A–September 2009–Revised March 2010

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