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EVM Assembly Drawings and Layout Guidelines

Figure 10. Layer-Three Routing

Figure 11. Bottom-Side Placement/Routing

7.2 Layout Guidelines

The layout of the PoE front end must follow power and EMI/ESD best practice guidelines. A basic set of

recommendations include:

• Parts placement must be driven by power flow in a point-to-point manner; RJ-45, Ethernet transformer,

diode bridges, TVS and 0.1-mF capacitor, and TPS23756 converter input bulk capacitor.

• All leads must be as short as possible with wide power traces and paired signal and return.

• There must not be any crossovers of signals from one part of the flow to another.

• Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input

voltage rails and between the input and an isolated converter output.

• The TPS23756 must be located over split, local ground planes referenced to VSS for the PoE input

and to RTN for the converter. Whereas the PoE side may operate without a ground plane, the

converter side must have one. Logic ground and power layers must not be present under the Ethernet

input or the converter primary side.

• Large copper fills and traces must be used on SMT power-dissipating devices, and wide traces or

overlay copper fills must be used in the power path.

SLVU329A–September 2009–Revised March 2010 TPS23756EVM

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