Datasheet

FRS
SW
17250
R (k ) =
f (kHz)
W
( )
( )
DT
DT
t ns
R k =
2
W
TPS23754
TPS23754-1
TPS23756
www.ti.com SLVS885G –OCTOBER 2008–REVISED OCTOBER 2013
Table 1. Class Resistor Selection
POWER AT PD
RESISTOR
CLASS NOTES
MINIMUM MAXIMUM
(Ω)
(W) (W)
0 0.44 13.0 1270 Minimum may be reduced by pulsed loading. Serves as a catch-all default class.
1 0.44 3.84 243
2 3.84 6.49 137
3 6.49 13.0 90.9
4 13.0 25.5 63.4 Not allowed prior to IEEE 802.3at. Use to indicate a Type 2 PD (high power)
device per IEEE 802.3at.
Current Sense (CS)
The CS input for the DC/DC converter should be connected to the high side of the switching MOSFET’s current
sense resistor (R
CS
). The current-limit threshold, V
CSMAX
, defines the voltage on CS above which the GATE ON
time will be terminated regardless of the voltage on CTL.
The TPS23754 device provides internal slope compensation (150 mV, V
SLOPE
), an output current for additional
slope compensation, a peak current limiter, and an off-time pull-down to this pin.
Routing between the current-sense resistor and the CS pin should be short to minimize cross-talk from noisy
traces such as the gate drive signal.
Control (CTL)
CTL is the voltage-control loop input to the pulse-width modulator (PWM). Pulling V
CTL
below V
ZDC
causes GATE
to stop switching. Increasing V
CTL
above V
ZDC
(0 duty cycle voltage) raises the switching MOSFET programmed
peak current. The maximum (peak) current is requested at approximately V
ZDC
+ (2 × V
CSMAX
). The AC gain from
CTL to the PWM comparator is 0.5. The internal divider from CTL to ARTN is approximately 100 kΩ.
Use V
B
as a pull-up source for CTL.
Detection and Enable (DEN)
DEN is a multifunction pin for PoE detection and inhibiting operation from PoE power. Connect a 24.9 kΩ resistor
from DEN to V
DD
to provide the PoE detection signature. DEN goes to a high-impedance state when V
VDD-VSS
is
outside of the detection range. Pulling DEN to V
SS
during powered operation causes the internal hotswap
MOSFET and class regulator to turn off, while the reduced detection resistance prevents the PD from properly
re-detecting.
DT
Dead-time programming sets the delay between GATE and GAT2 to prevent overlap of MOSFET ON times as
shown in Figure 2. GAT2 turns the second MOSFET off when it transitions high. Both MOSFETs should be off
between GAT2 going high to GATE going high, and GATE going low to GAT2 going low. The maximum GATE
ON time is reduced by the programmed dead-time period. The dead time period is specified with 1 nF of
capacitance on GATE and GAT2. Different loading on these pins changes the effective dead time.
A resistor connected from DT to ARTN sets the delay between GATE and GAT2 per Equation 3.
(3)
Connect DT to V
B
to set the dead time to 0 and turn GAT2 off.
Frequency and Synchronization (FRS)
Connect a resistor from FRS to ARTN to program the converter switching frequency. Select the resistor per the
following relationship.
(4)
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 9