Datasheet

PAD=V
SS
N/C=LeavePinUnused
TPS23754-1
1
2
3
4
5
6
7
15
14
13
11
12
8
16
V
DD
DEN
DT
FRS
CLS
GATE
RTN
V
C
CS
V
SS
V
B
CTL
T2P
BLNK
GAT2
10
9
19
18
17
20
PAD=V
SS
APD
ARTN
COM
TPS23754/6
PPD
V
DD1
1
2
3
4
5
6
7
15
14
13
11
12
8
16
V
DD
DEN
DT
FRS
CLS
GATE
RTN
V
C
CS
V
SS
V
B
CTL
T2P
BLNK
GAT2
10
9
19
18
17
20
APD
ARTN
COM
N/C
V
DD1
TPS23754
TPS23754-1
TPS23756
www.ti.com SLVS885G –OCTOBER 2008–REVISED OCTOBER 2013
(TOP VIEW)
PIN FUNCTIONS
NO.
TPS23754 TPS2375
NAME TYPE DESCRIPTION
and 4-1
TPS23756
APD 17 17 I Raising V
APD
– V
ARTN
above 1.5 V disables the internal hotswap switch, turns class off, and forces
T2P active. This forces power to come from a external V
DD1-RTN
adapter. Tie APD to ARTN when
not used.
ARTN 8 8 ARTN is the DC/DC converter analog return. Tie to RTN and COM on the circuit board.
BLNK 18 18 I Connect to ARTN to utilize the internally set current-sense blanking period, or connect a resistor
from BLNK to ARTN to program a more accurate period.
CLS 15 15 I Connect a resistor from CLS to V
SS
to program classification current. 2.5 V is applied to the
program resistor during classification to set class current.
COM 4 4 Gate driver return, connect to ARTN and RTN.
CS 3 3 I/O DC/DC converter switching MOSFET current sense input. See R
CS
in Figure 1.
CTL 1 1 I The control loop input to the pulse-width modulator (PWM), typically driven by output regulation
feedback (for example, optocoupler). Use V
B
as a pullup for CTL.
DEN 13 13 I/O Connect a 24.9 kΩ resistor from DEN to V
DD
to provide the PoE detection signature. Pulling this
pin to V
SS
during powered operation causes the internal hotswap MOSFET to turn off.
DT 16 16 I Connect a resistor from DT to ARTN to set the GATE to GAT2 dead time. Tie DT to V
B
to disable
GAT2 operation.
FRS 19 19 I Connect a resistor from FRS to ARTN to program the converter switching frequency. FRS may be
used to synchronize the converter to an external timing source.
GATE 5 5 O Gate drive output for the main DC/DC converter switching MOSFET.
GAT2 7 7 O Gate drive output for a second DC/DC converter switching MOSFET (see Figure 1).
NC – 14 Float this no-connect pin.
PAD – – Connect to V
SS
.
PPD 14 – I Raising V
PPD-VSS
above 1.55 V enables the hotswap MOSFET and activates T2P. Connecting
PPD to V
DD
enables classification when APD is active. Tie PPD to V
SS
or float when not used.
RTN 9 9 RTN is the output of the PoE hotswap MOSFET.
T2P 20 20 O Active low output that indicates a PSE has performed the IEEE 802.3at type 2 hardware
classification, PPD is active, or APD is active.
V
B
2 2 O 5.1-V bias rail for DC/DC control circuits and the feedback optocoupler. Typically bypass with a 0.1
μF to ARTN.
V
C
6 6 I/O DC/DC converter bias voltage. Connect a 0.47 μF (minimum) ceramic capacitor to ARTN at the
pin, and a larger capacitor to power startup.
V
DD
12 12 I Connect to the positive PoE input power rail. V
DD
powers the PoE interface circuits. Bypass with a
0.1 μF capacitor and protect with a TVS.
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