Datasheet

D
CLRB
Q
Oscillator
1
GATE
V
DD1
Reg
V
C
V
B
Ref
CTL
FRS
Control
enb
CONV.
OFF
+
-
4ms
Softstart
0.55V
-
+
-
CK
11V&
9V
22V&
21.25V
35V&
30.5V
Class
Logic&
Regulator
V
DD
50mW
1
0
S
R
Q
12.5V
&1V
ILIM
H
L
V
SS
Common
Circuitsand
PoE Thermal
Monitor
RTN
CLS
APD
V
SS
DEN
+
-
400ms
EN
2.5V
CONV.
OFF
4V
1.5V
&1.2V
ARTN
+
0.75V
PPD
GAT2
DT
COM
ARTN
T2P
ARTN
pa
sa
1.55V
&1.25V
ARTN
Converter
Thermal
Monitor
f
f
ss
t2
T2
State
Eng.
t2
5V
&4V
pa,sa,den
CTL
f
Deadtime
GlobalCvtr.
Enable
50kW
50kW
BLNK
ARTN
CS
40mA
(pk)
3.75kW
enb
Hotswap
MOSFET
Switch
Matrix
T2P Logic
fpd
7.8V
den
uvlo
uvlo, fpd
uvlo
t
DT1
GATEGAT2
50%
50%
t
DT2
time
lo
lo
hi
hi
TPS23754
TPS23754-1
TPS23756
SLVS885G –OCTOBER 2008–REVISED OCTOBER 2013 www.ti.com
Figure 2. GATE and GAT2 Timing and Phasing
DEVICE INFORMATION
FUNCTIONAL BLOCK DIAGRAM
6 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated