Datasheet

( )
2
2
DD SS
RPPD
PPD1 PPD2
24 V 1.1
(V V )
P = = = 19.6 mW
R + R 3.01 k + 32.4 k
´
-
W W
( )
( )
PPDEN PPDH
ADPTR_OFF PPDEN PPDH PPD1 PPD
PPD2
V V
V = V V + R I = 14.75 V
R
é ù
æ ö
-
- ´ +
ê ú
ç ÷
ç ÷
ê ú
è ø
ë û
PPDEN
ADPTR_ON PPDEN PPD1 PPD
PPD2
V
V = V + R I = 18.4 V
R
é ù
æ ö
´ +
ê ú
ç ÷
ê ú
è ø
ë û
ADPTR_ON PPDEN
PPD1
PPDEN
PPD
PPD2
V V
18 V 1.55 V
R = = = 31.64 k
V 1.55 V
5 A
I
3.01 k
R
æ ö
æ ö
ç ÷
ç ÷
-
-
ç ÷
W
ç ÷
ç ÷
ç ÷
+ m
+
ç ÷
ç ÷
W
è ø
è ø
TPS23754
TPS23754-1
TPS23756
SLVS885G –OCTOBER 2008–REVISED OCTOBER 2013 www.ti.com
Classification Resistor, R
CLS
Connect a resistor from CLS to V
SS
to program the classification current according to the IEEE 802.3at standard.
The class power assigned should correspond to the maximum average power drawn by the PD during operation.
Select R
CLS
according to Table 1.
For a high-power design, choose class 4 and R
CLS
= 63.4 Ω.
APD Pin Divider Network, R
APD1
, R
APD2
The APD pin can be used to disable the TPS23754 device internal hotswap MOSFET giving the adapter source
priority over the PoE source. An example calculation is provided, see literature number SLVA306A.
PPD Pin Divider Network, R
PPD1
, R
PPD2
The PPD pin can be used to override the internal hotswap MOSFET UVLO (V
UVLO_R
and V
UVLO_H
) when using
low voltage adapters connected between V
DD
and V
SS
. The PPD pin has an internal 5-μA pull-down current
source. As an example, consider the choice of R
PPD1
and R
PPD2
, for a 24-V adapter.
1. Select the startup voltage, V
ADPTR-ON
approximately 75% of nominal for a 24-V adapter. Assuming that the
adapter output is 24 V ± 10%, this provides 15% margin below the minimum adapter operating voltage.
2. Choose V
ADPTR-ON
= 24 V × 0.75 = 18 V.
3. Choose R
PPD2
= 3.01 kΩ.
4. Calculate R
PPD1
.
(a)
(b) Choose R
PPD1
= 32.4 kΩ.
5. Check PPD turn on and PPD turn off voltages.
(a)
(b)
(c) Voltages look acceptable.
6. Check PPD resistor power consumption.
(a)
(b) Power is acceptable, but resistor values could be increased to reduce the power loss.
The PPD pin can also be used to modify the internal MOSFET UVLO for use with a lower output voltage
PSE (within certain limits). Connect the R
PPD1
and R
PPD2
dividers directly between VDD and VSS with
the midpoint connected to PPD. For this case and to allow classification, target the minimum PSE OFF
voltage (V
ADPTR_OFF
) > V
CU_OFF
= 23 V. Then follow the procedure outlined above to select R
PPD1
, R
PPD2
,
and determine the PSE ON (V
ADPTR_ON
) and PSE OFF (V
ADPTR_OFF
) voltages ensuring that PSE OFF >
23 V. Lastly, since the R
PPD1
and R
PPD2
divider is in parallel with R
DEN
during detection, R
DEN
must be
increased such that the equivalent detection resistance is 25 kΩ nominal.
Setting Frequency (R
FRS
) and Synchronization
The converter switching frequency is set by connecting R
FRS
from the FRS pin to ARTN. The frequency may be
set as high as 1 MHz with some loss in programming accuracy as well as converter efficiency. Synchronization
at high duty cycles may become more difficult above 500 kHz due to the internal oscillator delays reducing the
available on-time. As an example:
1. Assume a desired switching frequency (f
SW
) of 250 kHz.
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