Datasheet

TPS23754
TPS23754-1
TPS23756
www.ti.com SLVS885G –OCTOBER 2008–REVISED OCTOBER 2013
The TPS23754 is optimized for isolated converters, and does not provide an internal error amplifier. Instead, the
optocoupler feedback is directly fed to the CTL pin which serves as a current-demand control for the PWM.
There is an offset of V
ZDC
(about 1.5 V) and 2:1 resistor divider between the CTL pin and the PWM. A V
CTL
below
V
ZDC
will stop converter switching, while voltages above (V
ZDC
+ (2 × V
CSMAX
)) will not increase the requested
peak current in the switching MOSFET. Optocoupler biasing design is eased by this limited control range.
Bootstrap Topology
The internal startup current source and control logic implement a bootstrap-type startup as discussed in “Startup
and Converter Operation.” The startup current source charges C
VC
from V
DD1
when the converter is disabled
(either by the PD control or the V
C
control) to store enough energy to start the converter. Steady-state operating
power must come from a converter (bias winding) output or other source. Loading on V
C
and V
B
must be minimal
while C
VC
charges, otherwise the converter may never start. The optocoupler will not load V
B
when the converter
is off for most situations, however care should be taken in ORing topologies where the output is powered when
PoE is off.
The converter will shut off when V
C
falls below its lower UVLO. This can happen when power is removed from
the PD, or during a fault on a converter output rail. When one output is shorted, all the output voltages fall
including the one that powers V
C
. The control circuit discharges V
C
until it hits the lower UVLO and turns off. A
restart will initiate, as described in Startup and Converter Operation, if the converter turns off and there is
sufficient V
DD1
voltage. This type of operation is sometimes referred to as hiccup mode, which provides robust
output short protection by providing time-average heating reduction of the output rectifier.
The bootstrap control logic disables most of the converter controller circuits except the V
B
regulator and internal
reference. Both GATE and GAT2 (assuming GAT2 is enabled) will be low when the converter is disabled. FRS,
BLNK, and DT will be at ARTN while the V
C
UVLO disables the converter. While the converter runs, FRS, BLNK,
and DT will be about 1.25 V.
The startup current source transitions to a resistance as (V
VDD1
– V
VC
) falls below 7 V, but will start the converter
from adapters within t
ST
. The lower test voltage for t
ST
was chosen based on an assumed adapter tolerance, but
is not meant to imply a hard cutoff exists. Startup takes longer and eventually will not occur as V
DD1
decreases
below the test voltage. The bootstrap source provides reliable startup from widely varying input voltages, and
eliminates the continual power loss of external resistors. The startup current source will not charge above the
maximum recommended V
VC
if the converter is disabled and there is sufficient V
DD1
to charge higher.
Current Slope Compensation and Current Limit
Current-mode control requires the addition of a compensation ramp to the sensed inductive (transformer or
inductor) current for stability at duty cycles near and over 50%. The TPS23754 device has a maximum duty cycle
limit of 78%, permitting the design of wide input-range flyback and active clamp converters with a lower voltage
stress on the output rectifiers. While the maximum duty cycle is 78%, converters may be designed that run at
duty cycles well below this for a narrower, 36-V to 57-V PI range. The TPS23754 device provides a fixed internal
compensation ramp that suffices for most applications.
The TPS23754 device provides internal, frequency independent, slope compensation (150 mV, V
SLOPE
) to the
PWM comparator input for current-mode control-loop stability. This voltage is not applied to the current-limit
comparator whose threshold is 0.55 V (V
CSMAX
). If the provided slope is not sufficient, the effective slope may be
increased by addition of R
S
per Figure 31. The additional slope voltage is provided by (I
SL-EX
× R
S
). There is also
a small DC offset caused by the about 2.5-μA pin current. The peak current limit does not have duty cycle
dependency unless R
S
is used. This makes it easier to design the current limit to a fixed value. See Current
Slope Compensation for more information.
The internal comparators monitoring CS are isolated from the IC pin by the blanking circuits while GATE is low,
and for a short time (blanking period) just after GATE switches high. A 440 Ω (max) equivalent pull-down on CS
is applied while GATE is low.
Blanking – R
BLNK
The TPS23754 device provides a choice between internal fixed and programmable blanking periods. The
blanking period is specified as an increase in the minimum GATE on time over the inherent gate driver and
comparator delays. The default period (see the ELECTRICAL CHARACTERISTICS) is selected by connecting
BLNK to RTN, and the programmable period is set with R
BLNK
.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 23