Datasheet

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t-Time-10ms/div
I
PI
V
DD
-RTN
V
C
-RTN
Inrush
V
OUT
PIPowered
Switchingstarts
T2P @output
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50V/div
TPS23754
TPS23754-1
TPS23756
www.ti.com SLVS885G –OCTOBER 2008–REVISED OCTOBER 2013
Maintain Power Signature
The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating
voltage is applied. A valid MPS consists of a minimum DC current of 10 mA (or a 10-mA pulsed current for at
least 75 ms every 325 ms) and an AC impedance lower than 26.3 kΩ in parallel with 0.05 μF. The AC
impedance is usually accomplished by the minimum operating C
IN
requirement of 5 μF. When either APD or DEN
is used to force the hotswap switch off, the DC MPS will not be met. A PSE that monitors the DC MPS will
remove power from the PD when this occurs. A PSE that monitors only the AC MPS may remove power from the
PD.
Startup and Converter Operation
The internal PoE undervoltage lockout (UVLO) circuit holds the hotswap switch off before the PSE provides full
voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and
classification. The converter circuits discharge C
IN
, C
VC
, and C
VB
while the PD is unpowered. Thus V
VDD
-V
RTN
will
be a small voltage just after full voltage is applied to the PD, as seen in Figure 23. The PSE drives the PI voltage
to the operating range once it has decided to power up the PD. When V
VDD
rises above the UVLO turn-on
threshold (V
UVLO-R
, about 35 V) with RTN high, the TPS23754 device enables the hotswap MOSFET with an
approximately 140-mA (inrush) current limit as seen in Figure 25. Converter switching is disabled while C
IN
charges and V
RTN
falls from V
VDD
to nearly V
VSS
, however the converter startup circuit is allowed to charge C
VC
(the bootstrap startup capacitor). Additional loading applied between V
VDD
and V
RTN
during the inrush state may
prevent successful PD and subsequent converter start-up. Converter switching is allowed if the PD is not in
inrush, OTSD is not active, and the V
C
UVLO permits it. Once the inrush current falls about 10% below the
inrush current limit, the PD current limit switches to the operational level (about 970 mA). Continuing the startup
sequence shown in Figure 25, V
VC
continues to rise until the startup threshold (V
CUV
, about 15 V or about 9 V) is
exceeded, turning the startup source off and enabling switching. The V
B
regulator is always active, powering the
internal converter circuits as V
VC
rises. There is a slight delay between the removal of charge current and the
start of switching as the softstart ramp sweeps above the V
ZDC
threshold. V
VC
falls as it powers both the internal
circuits and the switching MOSFET gates. If the converter control bias output rises to support V
VC
before it falls
to V
CUV
– V
CUVH
(about 8.5 V or about 5.5 V), a successful startup occurs. T2P in Figure 23 (Figure 1, V
T2P-OUT
)
becomes active within t
T2P
from the start of switching, indicating that a type 2 PSE or an adapter is plugged in.
Figure 25. Power Up and Start
If V
VDD
- V
VSS
drops below the lower PoE UVLO (V
UVLO-R
- V
UVLO-H
, about 30.5 V), the hotswap MOSFET is turned
off, but the converter will still run. The converter will stop if V
VC
falls below the converter UVLO (V
CUV
– V
CUVH
,
about 8.5 V or about 5.5 V), the hotswap is in inrush current limit, 0% duty cycle is demanded by V
CTL
(V
CTL
<
V
ZDC
, about 1.5 V), or the converter is in thermal shutdown.
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