Datasheet

TPS23754
TPS23754-1
TPS23756
www.ti.com SLVS885G –OCTOBER 2008–REVISED OCTOBER 2013
V
B
V
B
is an internal 5.1-V regulated DC/DC controller supply rail that is typically bypassed by a 0.1-μF capacitor to
ARTN. V
B
should be used to bias the feedback optocoupler.
V
C
V
C
is the bias supply for the DC/DC controller. The MOSFET gate drivers run directly from V
C
. V
B
is regulated
down from V
C
, and is the bias voltage for the rest of the converter control. A startup current source from V
DD1
to
V
C
is controlled by a comparator with hysteresis to implement the converter bootstrap startup. V
C
must be
connected to a bias source, such as a converter auxiliary output, during normal operation.
A minimum 0.47 μF-capacitor, located adjacent to the V
C
pin, should be connected from V
C
to COM to bypass
the gate driver. A larger total capacitance is required for startup to provide control power between the time the
converter starts switching and the availability of the converter auxiliary output voltage.
V
DD
V
DD
is the positive input power rail that is derived from the PoE source (PSE). V
DD
should be bypassed to V
SS
with a 0.1-μF capacitor as required by the IEEE standard. A transient suppressor diode (TVS), a special type of
Zener diode, such as SMAJ58A should be connected from V
DD
to V
SS
to protect against overvoltage transients.
V
DD1
V
DD1
is the DC/DC converter startup supply. Connect to V
DD
for many applications. V
DD1
may be isolated by a
diode from V
DD
to support PoE priority operation.
V
SS
V
SS
is the PoE input-power return side. It is the reference for the PoE interface circuits and has a current-limited
hotswap switch that connects it to RTN. V
SS
is clamped to a diode drop above RTN by the hotswap switch.
A local V
SS
reference plane should be used to connect the input bypass capacitor, TVS, R
CLS
, and the
PowerPad™. This plane becomes the main heatsink for the TPS23754.
V
SS
is internally connected to the PowerPAD.
PowerPad™
The PowerPad™ is internally connected to V
SS
. It should be tied to a large V
SS
copper area on the PCB to
provide a low-resistance thermal path to the circuit board. TI recommends that a clearance of 0.025” be
maintained between V
SS
, RTN, and various control signals to high-voltage signals such as V
DD
and V
DD1
.
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