Datasheet

TPS23753
SLVS853C –JUNE 2008–REVISED JANUARY 2010 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PRODUCT INFORMATION
(1)
DEVICE DUTY CYCLE PoE UVLO ON / HYST. PACKAGE MARKING
TPS23753 0 – 80% 35/4.5 PW (TSSOP-14) TP23753
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
Voltages are with respect to V
SS
(unless otherwise noted)
VALUE UNIT
V
DD
, V
DD1
, DEN, RTN
(2)
–0.3 to 100 V
V
DD1
to RTN –0.3 to 100 V
CLS
(3)
–0.3 to 6.5 V
V
I
Input voltage range [APD, BLNK
(3)
, CTL, FRS
(3)
, V
B
(3)
] to RTN –0.3 to 6.5 V
CS to RTN –0.3 to V
B
V
V
C
to RTN –0.3 to 19 V
GATE to RTN –0.3 to V
C
+ 0.3 V
Sourcing current V
B
Internally limited mA
Average sourcing or sinking current GATE 25 mA
RMS
HBM 2 kV
ESD rating
CDM 500 V
ESD – system level (contact/air)
(4)
8/15 kV
–40 to Internally
T
J
Operating junction temperature range °C
Limited
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) I
RTN
= 0 for V
RTN
> 80V.
(3) Do not apply voltage to these pins.
(4) Surges per EN61000-4-2, 1999 applied between RJ-45 and output ground and between adapter input and output ground of the
TPS23753EVM-001 (HPA304-001) evaluation module (documentation available on the web). These were the test levels, not the failure
threshold.
DISSIPATION RATINGS
Ψ
JT
θ
JA
θ
JA
PACKAGE
(°C/W)
(1)
(°C/W)
(2)
(°C/W)
(1)
PW (TSSOP-14) 0.97 173.6 99.3
(1) JEDEC method with high-k board (4 layers, 2 signal and 2 planes). T
J
= T
TOP
+ (Ψ
JT
x P
J
). Use Ψ
JT
to validate T
J
from measurements.
(2) JEDEC method with low-k board (2 signal layers).
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