Datasheet

EVM Assembly Drawings and Layout Guidelines

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7.2 Layout Guidelines

Follow power and EMI/ESD best practice guidelines for the layout of the PoE front end. A basic set of

recommendations include:

• Parts placement must be driven by power flow in a point-to-point manner; RJ-45, Ethernet transformer,

diode bridges, TVS and 0.1-μF capacitor, and TPS23752 converter input bulk capacitor.

• Make all leads as short as possible with wide power traces and paired signal and return.

• No crossovers of signals are allowed from one part of the flow to another.

• Observe spacing consistent with safety standards, like IEC60950, between the 48-V input voltage rails

and between the input and an isolated-converter output.

• Place the TPS23752 over split, local ground planes referenced to VSS for the PoE input and to RTN

for the converter. Whereas the PoE side may operate without a ground plane, the converter side must

have one. Make sure no logic ground and power layers are present under the Ethernet input or the

converter primary side.

• Use large copper fills and traces on SMT power-dissipating devices, and use wide traces or overlay

copper fills in the power path.

The DC/DC Converter layout benefits from basic rules, such as:

• Pair signals, reducing emissions and noise, especially the paths that carry high-current pulses which

include the power semiconductors and magnetics.

• Minimize the trace length of high current, power semiconductors, and magnetic components.

• Use vertical pairing, where possible.

• Use the ground plane for the switching currents carefully.

• Keep the high-current and high-voltage switching away from low-level sensing circuits, including those

outside the power supply.

• Maintain proper spacing around the high-voltage sections of the converter.

TPS23752EVM-145: Evaluation Module for TPS23752 SLVU753–July 2012

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