Datasheet
V
GATE
90% 90%
10%
Time
0
10%
t
prr10-90
t
pff90-10
50%
V
CS
Time
50%
V
GATE
0
0
Time
t
prf50-50
D
SLOPE_
ST
D
MAX
1
V
SLOPE
Voltage added to
current sense
Time normalized to
one switching cycle
V
SLOPE
= V
PK
/ (D
MAX
± D
SLOPE_ST
)
0,0
V
PK
TPS23751
TPS23752
www.ti.com
SLVSB97C –JULY 2012–REVISED JANUARY 2014
PoE INTERFACE SECTION (continued)
Unless otherwise noted, V
VC
= V
APD
= V
CS
= V
ARTN
= V
RTN
.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
THERMAL SHUTDOWN
Shutdown T
J
rising 135 145 155 °C
Hysteresis
(1)
20 °C
(1) Parameters provided for reference only, and do not constitute part of TI published specifications for purposes of TI product warranty.
Figure 2. Current Mode Compensation Ramp
Figure 3. Time Delay from V
CS
to V
GATE
Figure 4. Rise Time and Fall Time of V
GATE
DEVICE INFORMATION
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