Datasheet
C
GATE C SW GATE
QG
V
P V Q
V
æ ö
= ´ ¦ ´ ´
ç ÷
ç ÷
è ø
R
CS
GATE
CS
RTN
R
S
C
S
ARTN
R
VFF
VDD
( )
( )
PK
SLOPE _D
MAX SLOPE _ ST
S
CS _ RAMP
MAX SLOPE _ ST
V (mV)
V (mV)
D D
R ( ) 1000
I ( A)
D D
-
-
W = ´
m
-
TPS23751
TPS23752
SLVSB97C –JULY 2012–REVISED JANUARY 2014
www.ti.com
Current Slope Compensation
The TPS23751 and TPS23752 provide a fixed internal compensation ramp that suffices for most applications. R
S
(see Figure 30) may be used if the internally provided slope compensation is not enough. Most current-mode
control papers and application notes define the slope values in terms of V
PP
/T
S
(peak ramp voltage / switching
period). Assuming that the desired slope, V
SLOPE_D
(in mV/period), as shown in Figure 2, is based on the full
period, compute R
S
per the following equation where V
PK
and I
CS_RAMP
are from the electrical characteristics
table with voltages in mV and current in μA.
(5)
Figure 30. Additional Slope Compensation
C
S
may be required if the presence of R
S
causes increased noise, due to adjacent signals like the gate drive, to
appear at the C
S
pin.
Voltage Feed-Forward Compensation
Voltage feed-forward compensation can provide additional benefits including a flatter output fold-back current
limit characteristic (versus input voltage), and a reduction of voltage stress on the primary switching MOSFET at
high line and output overload. Voltage feed-forward can simply be applied by adding a resistor, R
VFF
between
VDD and CS as shown in Figure 30. The current through R
VFF
and R
S
provides a small dc offset on the CS pin
which reduces the output fold back current limit.
A simple way to choose R
VFF
is to first determine the natural circuit output fold back current at minimum line input
voltage. For example, if the circuit requirements are to deliver a regulated 5 V output at 5 A from a 24 V dc
adapter, then low line input could be as low as 21.6 V including tolerance. R
VFF
must be set large enough to
allow the required current to be delivered prior to output voltage fold back. Natural circuit output fold back current
and primary MOSFET voltage stress should also be characterized at high line in order to assess the
improvement provided by the addition of R
VFF
.
For a given SRT setpoint, the addition of R
VFF
reduces the output current at which the VFO to PWM (and PWM
to VFO) transition occurs. This requires that the designer increase V
SRT
to account for the reduction due to R
VFF
.
Estimating Bias Supply Requirements and Cvc
The bias supply (V
C
) power requirements determine C
VC
sizing and hiccup frequency during a fault. The first step
is to determine the power and current requirements of the power supply control circuitry, then select C
VC
. The
following example assumes that control current draw is constant with voltage with no loading by the feedback
and T2P optocouplers to simplify the process:
1. Let V
QG
be the gate voltage swing that the MOSFET Q
G
is rated to (often 10 V).
(6)
32 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: TPS23751 TPS23752