Datasheet

9 9
T
SW
8.5 10 8.5 10
R 34000
(Hz) 250000
´ W ´ W
= = = W
¦
SRT1 SRT
SRT2
B SRT
R V
100 k 0.5 V
R 11.1 k
V V 5 V 0.5 V
´
W ´
= = = W
- -
CTL
SRT CTL
Transition to VFO mode when V 2.0 V
V 2 V 3.5 V 2 2.0 V 3.5 V 0.5 V
=
= ´ - = ´ - =
TPS23751
TPS23752
www.ti.com SLVSB97C –JULY 2012–REVISED JANUARY 2014
Protection, D
1
A TVS, D
1
, across the rectified PoE voltage per Figure 1 must be used. A SMAJ58A, or equivalent, is
recommended for general indoor applications. Adequate capacitive filtering or a TVS must limit input transient
voltage to within the absolute maximum ratings. Outdoor transient levels or special applications require additional
protection.
Capacitor, C
1
The IEEE 802.3at standard specifies an input bypass capacitor (from V
DD
to V
SS
) of 0.05 μF to 0.12 μF. Typically
a 0.1 μF, 100 V, 10% ceramic capacitor is used.
Detection Resistor, R
DEN
The IEEE 802.3at standard specifies a detection signature resistance, R
DEN
between 23.75 kΩ and 26.25 kΩ, or
25 kΩ ± 5%. A resistor of 24.9 kΩ ± 1% is recommended for R
DEN
.
Classification Resistor, R
CLS
Connect a resistor from CLS to V
SS
to program the classification current according to the IEEE 802.3at standard.
The class power assigned should correspond to the maximum average power drawn by the PD during operation.
Select R
CLS
according to Table 1. For a high power design, choose class 4 and R
CLS
= 63.4 Ω.
APD Pin Divider Network, R
APD1
, R
APD2
The APD pin can be used to disable the TPS23751 and TPS23752 internal hotswap MOSFET, giving the
adapter source priority over the PoE. For an example calculation, see literature number SLVA306A.
Setting the PWM-VFO Threshold using the SRT pin
The TPS23751 and TPS23752 internally compares modified voltages at the SRT and CTL pins to determine the
operating mode. The designer should consider the light load operating point (considering the value of V
CTL
)
where synchronous rectifier (M2 in Figure 29) gate drive and switching losses nearly match conduction losses of
the rectifier diode (D
OUT
in Figure 29). Typically, the designer characterizes circuit efficiency, output load, and
control pin (V
CTL
) voltage and then select the transition point. Both VFO → PWM (occurs at higher load current
due to natural hysteresis) and PWM → VFO (occurs at slightly lower load current) transitions should be
considered when choosing the V
SRT
setpoint. As an example:
1. Assume that the desired efficiency transition threshold occurs at 18% of full load and V
CTL
= 2.0 V
2. Determine where to set V
SRT
.
(2)
3. Set V
SRT
using a voltage divider from V
B
to ARTN as shown in Figure 29.
4. Choose R
SRT1
= 100 kΩ and then calculate R
SRT2
as follows:
(3)
5. Select 11 kΩ for R
SRT2
.
Setting Frequency (R
T
)
The converter switching frequency in PWM mode is set by connecting resistor, R
T
from the RT pin to ARTN (see
Figure 29). The frequency may be set as high as 1 MHz with some loss in programming accuracy as well as
converter efficiency. As an example:
1. Assume a desired switching frequency (f
SW
) of 250 kHz.
2. Compute R
T
:
(4)
3. Select 34 kΩ for R
T
.
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