Datasheet

TPS23751
TPS23752
www.ti.com SLVSB97C –JULY 2012–REVISED JANUARY 2014
(S
WAKE
in Figure 29) is monitored by the WAKE pin and the latched sleep state exits when the button is pressed.
The button is connected to ARTN through an optocoupler LED (OPTO6 in Figure 29) that alerts the device
controller the button was pushed during normal operation. The MODE pin also has a second function, serving to
activate the LED output when driven low during normal converter operation. For more information regarding the
TPS23752 Sleep Mode Feature, see TPS23752 Maintain Power Signature Operation In Sleep Mode (SLVA588).
Converter Controller Features
The TPS23751 and TPS23752 DC-DC controller implements typical current-mode control as well as variable
frequency operation for light load efficiency optimization as shown in the Functional Block Diagram. Features
include programmable oscillator, over-current, PWM, VFO, and ZDC comparators, current-sense blanker,
softstart, and gate driver. In addition, an internal slope-compensation ramp generator, thermal shutdown, and
startup current source with control are provided.
The TPS23751 and TPS23752 are targeted at high efficiency, current mode, synchronous, flyback converters
incorporating an external error amplifier. In PWM mode, the external error amplifier and optocoupler drives the
CTL pin to demand current from the PWM. The internal current sense to control (CS to CTL pin) gain is 5V/V.
VFO mode can be enabled using a voltage divider on the SRT pin. The TPS23751 and TPS23752 enter VFO
mode when V
CTL
falls below V
SRT
/2 + 1.75V.
PWM and VFO Operation; CTL, SRT, and SRD Pin Relationships to Output Load Current
As the TPS23751 and TPS23752 transition from PWM to VFO mode with decreasing output load current, several
things happen to help reduce the light load losses of the DC-DC converter. A summary is shown in Table 3.
Table 3. Comparison of PWM and VFO Modes
SYNCHRONOUS RECTIFIER INTERNAL SLOPE
MODE SWITCHING FREQUENCY INDUCTOR PEAK CURRENT
(control with SRD pin) COMPENSATION
PWM Constant; set by R
T
Variable, set by V
CTL
Enabled (SRD = LOW) Enabled
VFO Variable; set by V
CTL
Constant, clamped by V
SRT
Disabled (SRD = OPEN) Disabled
The state of the SRD pin depends on the internal operating mode (PWM or VFO) and is used to enable or
disable the synchronous rectifier. In addition to disabling the synchronous rectifier, the TPS23751 and TPS23752
reduce the switching frequency in VFO mode to maintain output regulation.
Synchronous rectification provides an efficiency advantage over a standard diode rectifier at medium to heavy
loads, but not at lighter loads. The SRD feature can provide a means to recover the light load losses by disabling
the synchronous rectifier and allowing the standard diode rectifier to take over as illustrated in Figure 26 by the
VFO/PWM mode efficiency curve.
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