Datasheet
Time: 20ms/div
5V/div
100mA/div
I
PI
Inrush
Converter Starts
V
(VDD-RTN)
PI Powered
V
(VC-RTN)
Type 2 PSE
Type 1 PSE
T2P @ OUTPUT
OUTPUT VOLTAGE
50V/div
5V/div
5V/div
TPS23751
TPS23752
www.ti.com
SLVSB97C –JULY 2012–REVISED JANUARY 2014
Figure 24. Power Up and Start
If V
VDD
- V
VSS
drops below the lower PoE UVLO (V
UVLO-R
- V
UVLO-H
, approximately 32 V), the hotswap MOSFET is
turned off, but the converter still runs. The converter stops if V
VC
falls below the converter UVLO (V
CUV
– V
CUVH
,
approximately 5.7 V), the hotswap is in inrush current limit, 0% duty cycle is demanded by V
CTL
(V
CTL
< V
ZDC
,
approximately 1.75 V), or the converter is in thermal shutdown.
PD Hotswap Operation
IEEE 802.3at has taken a new approach to PSE output limiting. A type 2 PSE must meet an output current
versus time template with specified minimum and maximum sourcing boundaries. The peak output current may
be as high as 50 A for 10 μs or 1.75 A for 75 ms. This makes robust protection of the PD device even more
important than it was in IEEE 802.3-2008.
The internal hotswap MOSFET is protected against output faults and input voltage steps with a current limit and
deglitched (time-delay filtered) foldback. An overload on the pass MOSFET engages the current limit, with V
RTN
-
V
VSS
rising as a result. If V
RTN
rises above approximately 12 V for longer than approximately 800 μs, the current
limit reverts to the inrush value, and turns the converter off. The 800 μs deglitch feature prevents momentary
transients from causing a PD reset, provided that recovery lies within the bounds of the hotswap and PSE
protection. Figure 25 shows an example of recovery from a 16 V PSE rising voltage step. The hotswap MOSFET
goes into current limit, overshooting to a relatively low current, recovers to approximately 1000 mA full current
limit and charges the input capacitor while the converter continues to run. The MOSFET did not go into foldback
because V
RTN
-V
VSS
was below 12 V after the 800 μs deglitch.
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