Datasheet
9
SW
T
8.5 10
Hz
R
´ W
¦ =
TPS23751
TPS23752
www.ti.com
SLVSB97C –JULY 2012–REVISED JANUARY 2014
RT (Timing Resistor): A timing resistor (R
T
in Figure 1) connected between this pin and ARTN sets the PWM
switching frequency f
SW
according to Equation 1.
(1)
The switching frequency remains constant during PWM operation, but decreases as V
CTL
falls below V
CTL_VFO
.
RT is a high impedance pin. Keep the connections short and isolate them from potential noise sources.
RTN: The RTN pin provides the negative power return path for the converter. Once V
DD
exceeds the UVLO
threshold (V
UVLO_R
), the internal pass MOSFET pulls RTN to VSS. Inrush limiting prevents the RTN current from
exceeding about 140 mA until the bulk capacitance (C
IN
in Figure 1) is fully charged. Inrush ends and the
converter begins operating when the RTN current drops below about 125 mA. The RTN current is subsequently
limited to about 1 A. If RTN ever exceeds about 12 V, then the controller returns to inrush limiting.
RTN should be connected to ARTN for most applications.
SLPb: (TPS23752 only): The SLPb pin controls entry into Sleep Mode. A falling-edge transition applied to this
pin during normal operation initiates Sleep Mode. This mode of operation disables converter switching, increases
the current limit of the internal V
C
regulator, and pulls the LED output low. Cycling V
DD
or pulling the WAKE pin
low terminates the Sleep Mode and restores normal operation.
SRD (Synchronous Rectifier Disable): This open-drain output pulls to ARTN whenever the DC-DC converter is
enabled, inrush and soft start are complete, and the voltage at the CTL pin exceeds the threshold V
CTL_VFO
set
by the SRT pin. A low voltage on the SRD pin signals the synchronous rectifier to begin operation. If the CTL pin
voltage drops below V
CTL_VFO
, then the SRD output goes high impedance to disable the synchronous rectifier.
This action ensures that the synchronous rectifier does not operate during VFO mode.
SRT (Synchronous Rectifier Threshold): The SRT pin sets the thresholds V
CTL_VFO
and V
CS_VFO
, at which the DC-
DC converter switches between PWM and VFO. The application circuit normally uses a resistor divider
(R
SRT1
–R
SRT2
in Figure 1) to generate a voltage of 0.5 to 1.5 V at the SRT pin. When the voltage on the CTL pin
exceeds V
CTL_VFO
, the converter operates in PWM mode and the SRD pin is pulled low to enable the
synchronous rectifier. When the voltage on CTL falls below V
CTL_VFO
, the converter operates in VFO and the
SRD pin goes high impedance to disable the synchronous rectifier. Tying SRT to ARTN disables the VFO mode.
T2P (Type-2 PSE Indicator): The controller pulls this pin to ARTN whenever type-2 hardware classification has
been observed; or the APD pin is pulled high, after the internal T2P delay is complete, and V
CTL
≤ 4 V. Once T2P
is valid, V
CTL
has no effect on the status of T2P. The T2P output will return to a high-impedance state if the part
enters thermal shutdown, the pass MOSFET enters inrush limiting, or if a type-2 PSE was not detected and the
voltage on APD drops below its threshold. The circuitry that watches for type-2 hardware classification latches its
result when the V
(VDD-VSS)
voltage differential rises above the upper classification threshold. This circuit resets
when the V
(VDD-VSS)
voltage differential drops below the mark threshold. The T2P pin can be left unconnected if it
is not used.
V
B
(Bias Voltage): The V
B
pin is the output of an internal 5 V regulator fed from V
C
. A ceramic bypass capacitor
with a minimum capacitance of no less than 80 nF must connect from V
B
to ARTN. V
B
may be used to bias the
feedback optocoupler. For the TPS23752, V
B
may also bias pullups for SLPb and MODE.
V
C
(Controller Voltage): The V
C
pin connects to the auxiliary bias supply for the DC-DC controller. The MOSFET
gate driver draws current directly from V
C
. V
B
is regulated down from V
C
to provide power for the rest of the
internal control circuitry. A startup current source from V
DD
to V
C
controlled by a comparator with hysteresis
implements the converter bootstrap startup. V
C
must receive power from an auxiliary source, such as an auxiliary
winding on the flyback transformer, to sustain normal operation after startup. A low-ESR bypass capacitor, such
as a ceramic capacitor, must connect from V
C
to ARTN to supply the gate drive current required to drive the
external switching MOSFET.
The TPS23752 regulates V
C
to 12.8 V while in Sleep Mode to regulate the brightness of the Sleep-Mode LED.
The Sleep Mode output voltage is high enough to drive at least three LED’s in series when additional brightness
is required. This reduces the required value of R
LED
and associated power consumption for a given LED bias
current.
V
DD
: The V
DD
pin connects to the positive side of the input supply. The V
DD
pin provides operating power to the
PD controller, allows this circuit to monitor the input line voltage, and serves as the source for DC-DC startup
current. In the TPS23752, it also supplies the LED and MPS current during Sleep-Mode operation
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