Datasheet
TPS23751
TPS23752
SLVSB97C –JULY 2012–REVISED JANUARY 2014
www.ti.com
Table 1. Class Resistor Selection
MINIMUM POWER MAXIMUM POWER RESISTOR
CLASS
at PD (W) at PD (W) R
CLS
(Ω)
0 0.44 12.95 1270
1 0.44 3.84 243
2 3.84 6.49 137
3 6.49 12.95 90.9
4 12.95 25.5 63.4
CS (Current Sense): The CS pin serves as the current sense input for the DC-DC controller. The CS pin senses
the voltage at the high side of the current sense resistor (R
CS
in Figure 1). This voltage drives the current limit
comparator and the PWM comparator (see Block Diagram of DC-DC controller). A leading-edge blanking circuit
prevents MOSFET turn-on transients from falsely triggering either of these comparators. During the off time, and
also during the blanking time that immediately follows, the CS pin is pulled to ARTN through an internal pull-
down resistor.
The current limit comparator terminates the on-time portion of the switching cycle as soon as V
CS
exceeds
approximately 250 mV and the leading edge blanking interval has expired. If the converter is not in current limit,
then either the PWM comparator or the maximum duty cycle limiting circuit terminates the on time.
An internal slope compensation circuit generates a current that imposes a voltage ramp at the positive input of
the PWM comparator to suppress sub-harmonic oscillations. This current flows out of the CS pin. If desired, the
magnitude of the slope compensation can be increased by the addition of an external resistor in series with the
CS pin. The beginning of the slope compensation ramp is delayed to provide a smoother transition from PWM to
VFO mode, as shown in Figure 2. Slope compensation, including that generated by any external resistance, is
disabled in VFO mode.
CTL (Control): The CTL pin receives the control voltage from the external error amplifier. Typically this error
amplifier consists of a TL431 shunt regulator driving an optocoupler, but other configurations are possible. The
voltage differential between CTL and ARTN regulates power flow through the DC-DC converter. The voltage
V
CTL_VFO
set by the SRT pin represents the boundary between PWM and VFO mode. In the PWM mode of
operation, the CTL voltage determines the threshold at which the PWM comparator terminates the on-time
interval. During VFO mode, the inductor peak current is fixed and the CTL voltage varies the switching
frequency. During PWM mode the switching frequency is fixed and the CTL voltage varies the duty cycle.
DEN (Detection and Enable): The DEN pin implements two separate functions. A resistor (R
DEN
in Figure 1)
connected between V
DD
and DEN generates a detection signature whenever the voltage differential between V
DD
and V
SS
lies between approximately 1.4 and 10.9V. Beyond this range, the controller disconnects this resistor to
save power. For applications that wish to comply with the requirements of IEEE802.3at, the external resistance
should equal 24.9 kΩ.
If the resistance connected between V
DD
and DEN is divided into two roughly equal portions, then the application
circuit can disable the PD by grounding the tap point between the two resistances. This action simultaneously
spoils the detection signature and thereby signals the PSE that the PD no longer requires power.
GATE: The gate drive pin drives the main switching MOSFET of the DC-DC converter. The internal gate driver
circuitry draws power from V
C
and returns it to ARTN. GATE is held low whenever the converter is disabled.
LED (TPS23752 only): The LED pin drives an external status LED. Connect the LED and its series current-
limiting resistor from V
C
to the LED pin. While in Sleep Mode, the controller pulls the LED pin to ARTN. The LED
pin is also pulled low during normal operation after the soft start is complete whenever the MODE pin is low. The
LED pin should draw as little current as possible to help minimize the power consumed by the PD in Sleep
Mode. If a status LED is not required, leave this pin open.
MODE (TPS23752 only): The MODE pin in combination with the SLPb pin sets the type of MPS (DC or pulsed)
during Sleep Mode. Holding this pin high when the SLPb pin transitions low causes the TPS23752 to generate a
DC MPS by drawing a total of 10.6 mA (typical) from the Ethernet cable. Holding this pin low when the SLPb pin
transitions low causes the TPS23752 to generate a pulsed MPS. Either MPS ensures that the PSE does not
disconnect power from the PD while it is asleep. An MPS is not generated if the APD pin is held high (> 1.5 V).
During normal operation, pulling MODE low causes the LED pin to pull low.
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