Datasheet

1
SLPb
MPS
MODE
R
WKPLUP
Oscillator
1
Sleep
Frequency
Divider
Soft Start
Complete
Sleep
MPS
V
B
WAKE
Sleep
APD
MPS
+
Sleep
V
REF
LED
V
C
ARTN
V
B
Sleep
Sleep
Iref
MPS
Regulator
D
CLR
CLK
Q
Q
D
CLR
CLK
Q
Q
D
CLR
CLK
Q
Q
TPS23751
TPS23752
www.ti.com SLVSB97C –JULY 2012–REVISED JANUARY 2014
SLEEP MODE FUNCTIONALITY (TPS23752 ONLY)
PIN DESCRIPTION
The following descriptions refer to the schematic of Figure 1 and the Functional Block Diagrams.
APD: (Auxiliary Power Detect): The APD pin is used in applications that may draw power either from the
Ethernet cable or from an auxiliary power source. A voltage of more than about 1.5 V on the APD pin relative to
RTN turns off the internal pass MOSFET, disables the CLS output, and enables the T2P output. A resistor
divider (R
APD1
–R
APD2
in Figure 1) provides system-level ESD protection for the APD pin, discharges leakage from
the blocking diode (D
A
in Figure 1), and provides input voltage supervision to ensure that switch-over to the
auxiliary voltage source does not occur at excessively low voltages. If not used, connect APD to ARTN. When
the TPS23752 operates in Sleep Mode, holding APD higher than its rising threshold, V
APDEN
, disables the
maintain power signature (MPS).
ARTN: The ARTN pin is the local ground return for the DC-DC controller. Connections to the ARTN pin should
return to a local ground plane beneath the DC-DC converter primary circuitry. For most applications, this ground
plane should also connect to RTN.
CLS: An external resistor (R
CLS
in Figure 1) connected between the CLS pin and V
SS
provides a classification
signature to the PSE. The controller places a voltage of approximately 2.5 V across the external resistor
whenever the voltage differential between V
DD
and V
SS
lies between about 10.9 V and 22 V. The current drawn
by this resistor, combined with the internal current drain of the controller and any leakage through the internal
pass MOSFET, creates the classification current. Table 1 lists the external resistor values required for each of
the PD power ranges defined by IEEE802.3at. The maximum average power drawn by the PD, including all
losses within the DC-DC converter as well as power supplied to the downstream load, should not exceed the
maximum power indicated in Table 1. Holding APD high disables the classification signature.
High-power PSEs may perform two classification cycles if Class 4 is presented on the first cycle.
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