Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsDev KitsPCB design board

TPS23751

VC1

GATE

RTN

CTL

58V

0.1uF

DEN

From Ethernet

Pairs 1,2

From Ethernet

Pairs 3,4

CLS

DEN

T2P

CLS

Type 2 PSE

Indicator

FBU

FBL

TLV431

OUT

PAD

SRD

T2P

APD2

APD1

Adapter

SRT1

APD

SRT2

OUT

CTL

SRD

OUT

SRT

ARTN

OPTO2

OPTO1

OPTO3

TPS23751

TPS23752

www.ti.com

SLVSB97C –JULY 2012–REVISED JANUARY 2014

IEEE 802.3at PoE Interface with Wide Range High Efficiency DC-DC Controller

Check for Samples: TPS23751, TPS23752

FEATURES

DESCRIPTION

The TPS23751 is a 16-pin integrated circuit that

• IEEE 802.3at Classification with Status Flag

combines a Power-over-Ethernet (PoE) powered

• High Efficiency Solutions over Wide Load

device (PD) interface and a current-mode DC-DC

Range

controller optimized specifically for applications

• Powers up to 25.5 W PDs

requiring high efficiency over a wide load range.

• Robust 100 V, 0.5 Ω Hotswap MOSFET

The PoE interface implements type-2 hardware

classification per IEEE 802.3at. It also includes an

• Synchronous Rectifier Disable Signal

auxiliary power detect (APD) input and a disable

• PowerPAD™ TSSOP Packages

function (DEN). A 0.5 Ω, 100 V pass MOSFET

• Complete PoE Interface Plus DC-DC Controller

minimizes heat dissipation and maximizes power

• Adapter ORing Support

utilization.

• Programmable Frequency

The DC-DC controller features internal soft-start, a

bootstrap startup current source, current-mode

• TPS23752 Supports Ultra-Low Power Sleep

control with slope compensation, blanking, and

Modes

current limiting. Efficiency is enhanced at light loads

• –40°C to 125°C Junction Temperature Range

by disabling synchronous rectification and entering

variable frequency operation (VFO).

APPLICATIONS

The TPS23752 is a 20-pin extended version of the

• IEEE 802.3at-Compliant Devices

TPS23751 with the addition of a Sleep Mode feature.

• Video and VoIP Telephones

Sleep Mode disables the converter to minimize power

consumption while still generating the Maintain Power

• Multiband Access Points

Signature (MPS) required by IEEE802.3at.

• Security Cameras

• Pico-Base Stations

Figure 1. Typical Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (47 pages)

PAGE 1
TPS23751 TPS23752 www.ti.com SLVSB97C – JULY 2012 – REVISED JANUARY 2014 IEEE 802.3at PoE Interface with Wide Range High Efficiency DC-DC Controller Check for Samples: TPS23751, TPS23752 FEATURES DESCRIPTION • • The TPS23751 is a 16-pin integrated circuit that combines a Power-over-Ethernet (PoE) powered device (PD) interface and a current-mode DC-DC controller optimized specifically for applications requiring high efficiency over a wide load range.
PAGE 2
TPS23751 TPS23752 SLVSB97C – JULY 2012 – REVISED JANUARY 2014 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TPS23751 TPS23752 www.ti.com SLVSB97C – JULY 2012 – REVISED JANUARY 2014 THERMAL INFORMATION THERMAL METRIC (1) TPS23751 TPS23752 TSSOP-16 TSSOP-20 θJA Junction-to-ambient thermal resistance 39.5 38.5 θJCtop Junction-to-case (top) thermal resistance 25.9 23.8 θJB Junction-to-board thermal resistance 21.1 25.6 ψJT Junction-to-top characterization parameter 0.7 0.7 ψJB Junction-to-board characterization parameter 20.8 20.3 θJCbot Junction-to-case (bottom) thermal resistance 2.
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TPS23751 TPS23752 SLVSB97C – JULY 2012 – REVISED JANUARY 2014 www.ti.com ELECTRICAL CHARACTERISTICS Unless otherwise noted, 40 V ≤ VDD ≤ 57 V; VCTL = VMODE = VSLPb = VB; VSRT = 0.5 V; VAPD = VCS = VARTN = VRTN; CLS, GATE, LED, SRD, T2P open; RWAKE = 392 kΩ; RDEN = 24.9 kΩ; RT = 34 kΩ; CVB = CVC = 0.1 µF; –40 ≤ TJ ≤ 125°C. Typical values are at 25°C. All voltages referred to VSS.
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TPS23751 TPS23752 www.ti.com SLVSB97C – JULY 2012 – REVISED JANUARY 2014 CONTROLLER SECTION (continued) VC = 12 V, VDEN = VVSS, VARTN = VRTN = VSS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT A GATE (GATE DRIVER) Peak source current GATE high, pulsed measurement 0.35 0.60 1.00 Peak sink current GATE low, pulsed measurement 0.70 1.00 1.
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TPS23751 TPS23752 SLVSB97C – JULY 2012 – REVISED JANUARY 2014 www.ti.com PoE INTERFACE SECTION Unless otherwise noted, VVC = VAPD = VCS = VARTN = VRTN. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3 5 12 µA 0.1 5 µA DEN (DETECTION AND ENABLE) Bias current DEN open, IVDD + IDEN + IRTN, VVDD = 10.1 V, not in mark DEN leakage current VDEN = VVDD = 57 V Detection current Disable threshold VPD_DIS IVDD + IDEN + IRTN, VVDD = 1.4 V 53.8 56.5 58.3 IVDD + IDEN + IRTN, VVDD = 10.
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TPS23751 TPS23752 www.ti.com SLVSB97C – JULY 2012 – REVISED JANUARY 2014 PoE INTERFACE SECTION (continued) Unless otherwise noted, VVC = VAPD = VCS = VARTN = VRTN. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 135 145 155 °C THERMAL SHUTDOWN Shutdown Hysteresis (1) TJ rising (1) 20 °C Parameters provided for reference only, and do not constitute part of TI published specifications for purposes of TI product warranty.
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TPS23751 TPS23752 SLVSB97C – JULY 2012 – REVISED JANUARY 2014 www.ti.
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TPS23751 TPS23752 www.ti.com SLVSB97C – JULY 2012 – REVISED JANUARY 2014 DEVICE FUNCTIONAL BLOCK DIAGRAMS DC-DC CONTROLLER SLEEP Voltage Regulator (TPS23752 only) VDD VC VB Regulator OSTD SLEEP Control CONV.ON Reference CONV.OFF VC RT VOSC Oscillator GATE 0 1 VOSC CTL 1 D Q CK CLR VFO ARTN ZDC COMP VFO COMP 80k VFO VZDC,VFO VFO. OFF 20k 0 VCS,VFO 1 PWM COMP VFO Soft Start ISLOPE 0.35 V VFO 0.35 V 1 Blanking Circuit 1 ILIMIT COMP 0.
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TPS23751 TPS23752 SLVSB97C – JULY 2012 – REVISED JANUARY 2014 www.ti.com PoE 12V & 10V VDD 22V & 21.25V 5V & 4V Detection Comp. Class Comp. 4V Class Comp. VSS Mark Comp. 2.5V REG. 800Ps 800Ps 12V APD Comp. APD DEN CLS VSS RTN Mark Comp Output 1.5V & 1.2V UVLO Comp Output ARTN S R Q Type 2 State Eng. 1 = inrush 0 = current limit R Inrush latch S 38.1V & 32V OTSD UVLO Comp. t2 Inrush limit 1 threshold Current limit 0 threshold Q CONV.
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TPS23751 TPS23752 www.ti.com SLVSB97C – JULY 2012 – REVISED JANUARY 2014 SLEEP MODE FUNCTIONALITY (TPS23752 ONLY) VB 1 D SLPb Q Sleep CLK D CLR Q Q MPS CLK CLR Q MODE LED 1 Sleep D Q CLK Iref RWKPLUP VB Sleep VC CLR Q Sleep WAKE Oscillator Soft Start Complete Frequency Divider MPS Sleep VREF MPS Regulator + Sleep APD MPS ARTN PIN DESCRIPTION The following descriptions refer to the schematic of Figure 1 and the Functional Block Diagrams.
PAGE 12
TPS23751 TPS23752 SLVSB97C – JULY 2012 – REVISED JANUARY 2014 www.ti.com Table 1. Class Resistor Selection CLASS MINIMUM POWER at PD (W) MAXIMUM POWER at PD (W) RESISTOR RCLS (Ω) 0 0.44 12.95 1270 1 0.44 3.84 243 2 3.84 6.49 137 3 6.49 12.95 90.9 4 12.95 25.5 63.4 CS (Current Sense): The CS pin serves as the current sense input for the DC-DC controller. The CS pin senses the voltage at the high side of the current sense resistor (RCS in Figure 1).
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TPS23751 TPS23752 www.ti.com SLVSB97C – JULY 2012 – REVISED JANUARY 2014 RT (Timing Resistor): A timing resistor (RT in Figure 1) connected between this pin and ARTN sets the PWM switching frequency fSW according to Equation 1. ¦ SW = 8.5 ´ 109 W Hz RT (1) The switching frequency remains constant during PWM operation, but decreases as VCTL falls below VCTL_VFO. RT is a high impedance pin. Keep the connections short and isolate them from potential noise sources.
PAGE 14
TPS23751 TPS23752 SLVSB97C – JULY 2012 – REVISED JANUARY 2014 www.ti.com VSS: The VSS pin connects to the negative rail of the input supply. It serves as a local ground for the PD control circuitry. The PowerPAD™ must connect to VSS to ensure proper operation. WAKE (TPS23752 only): The WAKE pin performs several functions. During Sleep Mode, it outputs a currentlimited 2.5V. Pushing the external pushbutton (SWAKE in Figure 29) during Sleep Mode connects the WAKE pin to optocoupler, OPTO6.
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TPS23751 TPS23752 www.ti.com SLVSB97C – JULY 2012 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE DEN BIAS CURRENT vs SUPPLY VOLTAGE 450 7 TA = −40°C TA = 25°C TA = 125°C 350 300 250 200 150 100 5 4 3 2 1 24 29 34 39 44 VDD (V) 49 54 0 57 2 4 6 8 G002 Figure 5. Figure 6. CS VFO PEAK VOLTAGE vs SRT VOLTAGE VC OPERATING CURRENT vs VC VOLTAGE 6.
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TPS23751 TPS23752 SLVSB97C – JULY 2012 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS (continued) VC BOOTSTRAP CURRENT SOURCE vs SUPPLY VOLTAGE CTL PWM/VFO THRESHOLD vs SRT VOLTAGE TA = 25°C CTL PWM/VFO Threshold (V) TA = −40°C TA = 25°C TA = 125°C 1.28 1.26 1.24 1.22 1.2 1.18 Switching Frequency (kHz) 2.6 VC = 8.6 V 12 16 20 24 28 32 VDD (V) 36 40 44 2.4 2.3 2.2 2.1 G008 SWITCHING FREQUENCY vs PROGRAMMABLE CONDUCTANCE 900 400 RT = 16.
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TPS23751 TPS23752 www.ti.com SLVSB97C – JULY 2012 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS (continued) rDS(on) vs TEMPERATURE MPS SUPPLY CURRENT vs LED CURRENT 10.8 10.75 MPS Supply Current (mA) 0.7 0.65 0.6 rDS(on) (Ω) 0.55 0.5 0.45 0.4 0.35 0.3 10.7 10.65 10.6 10.55 10.5 10.45 0.25 0.2 −40 TA = −40°C TA = 25°C TA = 125°C 10.4 −20 0 20 40 60 Temperature (°C) 80 100 10.35 120 0 2 4 6 8 ILED (mA) G013 Figure 17. 10 G014 Figure 18. MPS SUPPLY CURRENT vs SUPPLY VOLTAGE 10.
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TPS23751 TPS23752 SLVSB97C – JULY 2012 – REVISED JANUARY 2014 www.ti.com Type 2 PSEs are required to do type 1 hardware classification plus a (new) data-layer classification, or an enhanced type 2 hardware classification. Type 1 PSEs are not required to do hardware or data link layer (DLL) classification. A type 2 PD must do type 2 hardware classification as well as DLL classification. The PD may return the default, 13W current-encoded class, or one of four other choices.
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TPS23751 TPS23752 www.ti.com SLVSB97C – JULY 2012 – REVISED JANUARY 2014 Table 2. Comparison of Operational Limits Standard Power Loop Resistance (max) PSE Output Power (min) PSE Static Output Voltage (min) PD Input Power (max) Static PD Input Voltage Power ≤ 12.95W Power > 12.95W IEEE802.3at-2008 802.3at (Type 1) 20 Ω 15.4W 44V 12.95W 37V – 57V N/A 802.3at (Type 2) 12.5Ω 30W 50V 25.5W 37V – 57V 42.
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TPS23751 TPS23752 SLVSB97C – JULY 2012 – REVISED JANUARY 2014 www.ti.com PoE Startup Sequence The waveforms of Figure 22 demonstrate detection, classification, and startup from a PSE with type 2 hardware classification. The key waveforms shown are V(VDD-VSS), V(RTN-VSS), and IPI. IEEE 802.3at requires a minimum of two detection levels, two class and mark cycles, and startup from the second mark event. VRTN to VSS falls as the TPS23751 or TPS23752 charges CIN following application of full voltage.
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TPS23751 TPS23752 www.ti.com SLVSB97C – JULY 2012 – REVISED JANUARY 2014 Hardware Classification Hardware classification allows a PSE to determine the power requirements of a PD before powering, and helps with power management once power is applied. Type 2 hardware classification permits high power PSEs and PDs to determine whether the connected device can support high-power operation. A type 2 PD presents class 4 in hardware to indicate that it is a high-power device.
PAGE 22
TPS23751 TPS23752 SLVSB97C – JULY 2012 – REVISED JANUARY 2014 www.ti.com Inrush and Startup IEEE 802.3at has a startup current and time limitation, providing type 2 PSE compatibility for type 1 PDs. A type 2 PSE limits output current to between 400 mA and 450 mA for up to 75 ms after power-up (applying “48 V” to the PI) in order to mirror type 1 PSE functionality. The type 2 PSE supports higher output current after 75 ms.
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TPS23751 TPS23752 www.ti.com SLVSB97C – JULY 2012 – REVISED JANUARY 2014 V(VDD-RTN) 50V/div Converter Starts Inrush IPI 100mA/div PI Powered V(VC-RTN) 5V/div OUTPUT VOLTAGE 5V/div Type 1 PSE T2P @ OUTPUT 5V/div Type 2 PSE Time: 20ms/div Figure 24. Power Up and Start If VVDD- VVSS drops below the lower PoE UVLO (VUVLO-R - VUVLO-H, approximately 32 V), the hotswap MOSFET is turned off, but the converter still runs. The converter stops if VVC falls below the converter UVLO (VCUV – VCUVH, approximately 5.
PAGE 24
TPS23751 TPS23752 SLVSB97C – JULY 2012 – REVISED JANUARY 2014 www.ti.com Recovery from PI Dropout V(VDD-VSS) 20V/div CIN Completes Charge While Converter Operates IPI 500mA/div 16-V Input Step VRTN < 12V @ 800 s V(RTN-VSS) 10V/div Time: 200 s/div Figure 25. Response to Output Short Circuit The PD control has a thermal sensor that protects the internal hotswap MOSFET. Conditions like startup or operation into a VDD-to-RTN short cause high power dissipation in the MOSFET.
PAGE 25
TPS23751 TPS23752 www.ti.com SLVSB97C – JULY 2012 – REVISED JANUARY 2014 (SWAKE in Figure 29) is monitored by the WAKE pin and the latched sleep state exits when the button is pressed. The button is connected to ARTN through an optocoupler LED (OPTO6 in Figure 29) that alerts the device controller the button was pushed during normal operation. The MODE pin also has a second function, serving to activate the LED output when driven low during normal converter operation.
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TPS23751 TPS23752 SLVSB97C – JULY 2012 – REVISED JANUARY 2014 www.ti.com 90 VFO/PWM Mode 85 80 Efficiency (%) 75 70 PWM Mode Only 65 60 55 50 45 40 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Load Current (A) Figure 26. TPS23751 and TPS23752 Light Load Efficiency versus Mode Figure 27 illustrates operation through the VFO to PWM to VFO transitions. As load current increases, so does VCTL.
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TPS23751 TPS23752 www.ti.com SLVSB97C – JULY 2012 – REVISED JANUARY 2014 ILOAD Natural Hysteresis 1A/div VCTL VFO Mode PWM Mode VFO Mode 500mV/div VSRD 10V/div Time: 5ms/div Figure 27. Converter Mode Transition There is a natural load current hysteresis for ILOAD which can be seen in Figure 27 between the transition points. For increasing ILOAD, the transition current is slightly higher than for decreasing ILOAD.
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TPS23751 TPS23752 SLVSB97C – JULY 2012 – REVISED JANUARY 2014 www.ti.com Current Slope Compensation and Current Limit Current-mode control requires addition of a compensation ramp to the sensed inductive (transformer or inductor) current for stability at duty cycles near and over 50%. The TPS23751 and TPS23752 have a maximum duty cycle limit of 80%, permitting the design of wide input-range converters with lower voltage stress on the output rectifiers.
PAGE 29
TPS23751 TPS23752 SLVSB97C – JULY 2012 – REVISED JANUARY 2014 VPOE VDD RDEN + Low Voltage Output DEN CLS ± VSS Power Circuit TPS23751/2 RCLS D1 C1 From Spare Pairs From Ethernet or Transformers Transformers www.ti.com RTN Adapter Option 1 Adapter Option 2 Adapter Option 3 Figure 28. Oring Configurations The IEEE standards require that the Ethernet cable be isolated from ground and all other system potentials.
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TPS23751 TPS23752 SLVSB97C – JULY 2012 – REVISED JANUARY 2014 www.ti.com APPLICATION INFORMATION From Ethernet Pairs 1,2 The TPS23751 and TPS23752 support power supply topologies that require a single PWM gate drive with current-mode control. Figure 29 provides an example of a synchronous rectifier flyback converter. Selecting a converter topology along with a design procedure is beyond the scope of this applications section. Examples to help in programming the TPS23751 and TPS23752 are shown below.
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TPS23751 TPS23752 www.ti.com SLVSB97C – JULY 2012 – REVISED JANUARY 2014 Protection, D1 A TVS, D1, across the rectified PoE voltage per Figure 1 must be used. A SMAJ58A, or equivalent, is recommended for general indoor applications. Adequate capacitive filtering or a TVS must limit input transient voltage to within the absolute maximum ratings. Outdoor transient levels or special applications require additional protection. Capacitor, C1 The IEEE 802.
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TPS23751 TPS23752 SLVSB97C – JULY 2012 – REVISED JANUARY 2014 www.ti.com Current Slope Compensation The TPS23751 and TPS23752 provide a fixed internal compensation ramp that suffices for most applications. RS (see Figure 30) may be used if the internally provided slope compensation is not enough. Most current-mode control papers and application notes define the slope values in terms of VPP/TS (peak ramp voltage / switching period).
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TPS23751 TPS23752 www.ti.com SLVSB97C – JULY 2012 – REVISED JANUARY 2014 Compute gate drive power if VC is 12 V and QGATE is 17 nC 12 PGATE = 12 V ´ 250kHz ´ 17nC ´ = 61.2mW 10 (7) This equation illustrates why MOSFET QG should be an important consideration in selecting the switching MOSFETs. 2. Estimate the required bias current at some intermediate voltage during the CVC discharge. For the TPS23751 and TPS23752, 12 V provides a reasonable estimate.
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TPS23751 TPS23752 SLVSB97C – JULY 2012 – REVISED JANUARY 2014 www.ti.com T2P Pin Interface The T2P pin is an active-low, open-drain output which indicates that a high power source is available. An optocoupler can interface the T2P pin to circuitry on the secondary side of the converter. A high-gain optocoupler and a high-impedance (for example, CMOS) receiver are recommended.
PAGE 35
TPS23751 TPS23752 www.ti.com SLVSB97C – JULY 2012 – REVISED JANUARY 2014 From Regulated Output Voltage ROB RSS RFBU CIZ DSS CSS RFBL TLV431 Figure 33. Error Amplifier Soft Start Special Switching MOSFET Considerations Special care must be used in selecting the converter switching MOSFET. The TPS23751 and TPS23752 minimum switching MOSFET VGATE is approximately 5.5 V, which is due to the VC lower threshold.
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TPS23751 TPS23752 SLVSB97C – JULY 2012 – REVISED JANUARY 2014 www.ti.com REVISION HISTORY Changes from Original (July 2012) to Revision A • Page Changed from PRODUCT PREVIEW to PRODUCTION DATA ........................................................................................... 1 Changes from Revision A (August 2012) to Revision B Page • Added "THERMAL SHUTDOWN" to the CONTROLLER SECTION ....................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 10-Jan-2014 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 10-Jan-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS23751PWPR HTSSOP PWP 16 2000 330.0 12.4 TPS23752PWPR HTSSOP PWP 20 2000 330.0 16.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.9 5.6 1.6 8.0 12.0 Q1 6.95 7.1 1.6 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 10-Jan-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS23751PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 TPS23752PWPR HTSSOP PWP 20 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.