Datasheet

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REG.
1.5V
FB
COMP
GATE
RSP
AUX
COM
V
BIAS
+
+
−
RSN
OSC.
15kW
SEN
V
DD
PWM
COMP.
STATE
LATCH
GATE
DRIVER
DELAY
ERROR
AMP
CE
0.5V
UVLO
&
OVLO
EN ABLE
+
−
RUN
20kW
TMR
RUN
FREQ
50 Am
5 Am
COM
CE
CLK
CLK
CLK
D
R
Q
0.75V
SOFT
START
and
FAULT
CTL
REG.
CE
HI LO
BL
X4
CNTR.
CLK
ENABLE
V
BIAS
FAULT
COMP.
MODE
SENP
80kW
−
+
15kW
Translator
−
0.5V
0.27V
CURRENT
LIMITCOMP.
−
+
10V
Regulator
375 sm
0.08 W
−
+
−
+
11.3Vand
9.3V
−
+
V
DD
RTN
36mV
11.2mV
CLASS
DET
Current
limit
UVLO
RTN
0
1
CE
V
SS
−
+
−
+
20.5V
and
18V
21.9V
and
21.28V
1.5V
and
12V
39.3V
and
30.5V
Thermal
shutdown
0=Hot
Detect
Class
High
OTSD
RTN
RTN
RTN
UVLO
OTSD
OTSD
OTSD
UVLO
SMPS
SMPS
TPS23750
TPS23770
SLVS590B – JULY 2005 – REVISED FEBRUARY 2008
BLOCK DIAGRAM
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