Datasheet
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TLV431
V
BIAS
RTN
Low
Voltage
Output
+
−
Converter Output Stage
1.5V
FB COMP
+
+
−
MODE
Error
Amplifier
To V
DD
15k
SEN
SENP
15k
Translator
Soft
start
RTN
RTN
Part of TPS23750
80k
20k
PWM
Comparator
Softstart
From
Blanker
+
−
−
RSN
1.5V
FB COMP
+
+
−
15k
SEN
MODE
SENP
R
Z
15k
Translator
Low
Voltage
Output
R
LO
R
HI
+
−
Converter Power Stage
1.5V
C
Z
Soft
start
Error
Amplifier
To
V
DD
To
GATE
RTN, COM, RSN
Part of TPS23750
RSP
C
BYP
To PWM
Comparator
80k
20k
ADDITIONAL USES OF SENP AND SEN
TPS23750
TPS23770
SLVS590B – JULY 2005 – REVISED FEBRUARY 2008
Isolated PD converters that use an optocoupler, such as TL431-based circuits, should use the configuration of
Figure 33 . The MODE connection disables the internal error amplifier, rendering its output high impedance. A
primary-side PWM softstart is internally implemented when the error amplifier is disabled. The same gain of
0.2 V/V appears before the PWM comparator. The COMP pin is still monitored to implement hiccup in this
configuration.
Figure 33. Isolated Converter Configuration
The buck converter configuration is shown in Figure 34 . The loop regulates the voltage across R
LO
to 1.5 V. The
translator topology provides a gain of 1 V/V from V
SENP-SEN
to the 15 k Ω internal series resistor. The error
amplifier gain expression is (Z
COMP-FB
/ 15 k Ω ). The output divider and translator attenuate both the ac and dc
components, unlike the configuration of Figure 32 where the ac signal is not divided because the virtual ground
at the amplifier input cancels the effect of R
LO
. Addition of C
BYP
across R
HI
applies the full ac signal to the error
amplifier. The R
HI
C
BYP
corner frequency should be at least an octave lower than the R
Z
C
Z
zero frequency. This
method assures C
BYP
has little effect on standard loop design practices.
Figure 34. Buck Converter Configuration
The level translator inputs, SENP and SEN, are not limited to the buck application shown in Figure 34 . They may
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