Datasheet

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FEATURES

DESCRIPTION

APPLICATIONS

T P S 2 3 7 5 0

TLV431

TMR

BIAS

TMR

FREQ

GATE

COM

RSN

AUX

RSP

COMP

BIAS

SEN

5 8 V

0.1 Fm

DET

CLASS

DET

LowVoltage

Isolated

Output

BIAS

MODE

SENP

RTN

FromS

pare

Pairsor

Transformers

FromEthernet

Transformers

TPS23750

TPS23770

SLVS590B – JULY 2005 – REVISED FEBRUARY 2008

www.ti.com

INTEGRATED 100-V IEEE 802.3af PD AND DC/DC CONTROLLER

• Complete 802.3af PoE Interface

– Features derived from the TPS2375

The TPS23750 integrates the functionality of the

TPS2375 with a primary-side dc/dc PWM controller.

– 100 V, 0.6 Ω Internal Pass MOSFET

The designer can create a front-end solution for

– Standard and Legacy UVLO Choices

PoE-PD applications with minimum external

– Fixed 140 mA Inrush Limit

components. The TPS23770 is identical to the

TPS23750 with the exception of the undervoltage

• Primary Side DC/DC Converter Control

lockout turn-on voltage, which is compatible with

– Minimum External Component Count

legacy systems.

– Current Mode Control

The PoE front end has all the necessary IEEE

– Isolated and Non-Isolated Topologies

802.3af functions including detection, classification,

– Programmable Operating Frequency

undervoltage lockout and inrush control. The PoE

input switch is integrated within the TPS23750.

– Current Sense Leading-edge Blanking

– 50% Duty Cycle Limiting

The dc/dc controller section is designed to support

flyback, forward, and nonsynchronous low-side switch

– Voltage Output Error Amplifier

buck topologies.

• Internal PoE and Converter Sequencing

The external switching MOSFET and current sense

• Industry-Standard 20 Lead Package

resistor provide flexibility in topology, power level, and

• Industrial Temperature Range: – 40 ° C to 85 ° C

current limit. The full-featured dc/dc controller

includes programmable soft start, hiccup type fault

limiting, 50% maximum duty cycle, programmable

constant switching frequency, and a true

• All PoE PD Devices Including:

voltage-output error amplifier. Additional protection

– Wireless Access Points

features provide for robust designs.

– VoIP Phones

– Security Cameras

Figure 1. Typical Application

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (41 pages)

PAGE 1
TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 INTEGRATED 100-V IEEE 802.3af PD AND DC/DC CONTROLLER FEATURES 1 DESCRIPTION • Complete 802.3af PoE Interface – Features derived from the TPS2375 – 100 V, 0.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 RECOMMENDED OPERATING CONDITIONS (1) (2) All voltage values are with respect to VSS unless otherwise noted. MIN VDD Input voltage range (3) Input voltage range Sourcing current QG NOM MAX COM, SEN, SENP 0 67 FB, COMP, MODE, BL 0 VBIAS AUX to COM 0 16 RSP to RSN 0 1 AUX 0 2 VBIAS 0 2 COMP 0 2 GATE loading UNIT V V mA 20 nC µF AUX load capacitance 0.8 25 VBIAS load capacitance 0.08 1.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 ELECTRICAL CHARACTERISTICS Characteristics are for: –40°C ≤ TJ ≤ 125°C; VDD – VSS = 48 V. VDD, CLASS, and DET referenced to VSS, and all other pin voltages are referenced to RSN, COM, and RTN shorted together unless otherwise noted. SEN=MODE=BL=RSP=RTN, FB=VBIAS, SENP=VDD, CTMR = 1000 pF, CVBIAS = 0.1 µF, CVAUX = 0.1 µF, RFREQ = 150 kΩ, RDET = 24.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 DC/DC CONTROLLER SECTION (continued) RTN = VSS for this section only. PARAMETER TEST CONDITIONS Translator output resistance VSENP-SEN = 1.5 V, TMR = RSN, IFB = 0 µA and 10 µA, RFB = ΔVFB / Δ IFB SEN sinking current VSENP-SEN = 1.50 V, VTMR = RSN SENP sinking current VSENP-SEN = 1.50 V, VTMR = RSN MIN TYP MAX UNIT 11.25 15 18.75 kΩ 1 µA 17 22.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 ELECTRICAL CHARACTERISTICS – COMBINED PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BIAS CURRENT IVDDQ Quiescent current Operational current Off state current 1 1.3 COMP = FB 1.1 1.4 mA COMP = FB, RFREQ = 30 kΩ 1.3 1.75 RTN = COM = RSN = VDD, VDD = 33 V 0.18 0.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 DEVICE INFORMATION TMR FB COMP SEN NC SENP VDD DET CLASS VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 FREQ BL VBIAS MODE AUX GATE COM RSN RSP RTN Figure 2. Pinout TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION TMR 1 O Multifunction pin, serves as a converter soft start and a hiccup timer. A capacitor to RTN determines the softstart and hiccup timing. FB 2 I Converter error amplifier inverting input.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 BLOCK DIAGRAM FREQ REG. CE SENP V BIAS Translator SEN OSC. CLK ENABLE 15 kW V DD HI STATE LATCH V BIAS 80 kW + − − + + − FB UVLO & OVLO CE LO RUN ERROR AMP 1.5 V AUX REG. PWM COMP. EN ABLE 15 kW COM GATE DRIVER D Q CLK GATE R COM COMP 0.27 V 0.5 V MODE 50 mA CURRENT LIMIT COMP. − 0.5 V BL CLK DELAY + RSP TMR FAULT COMP. 20 kW SOFT START and FAULT CTL X4 CNTR. CLK 0.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 DETAILED DESCRIPTION AUX – This pin is the junction between the internal 10 V converter-bias regulator, the gate driver supply, and the 5-V regulator that powers the rest of the converter control circuit. Voltage may be applied to this pin during normal converter operation to improve efficiency and reduce the TPS23750 temperature rise. A UVLO of about 8 V monitors VAUX-COM to prevent operation with inadequate or weak bias.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 The COMP output should not be over-driven when the internal error amplifier is active. The amplifier can source and sink significant currents which will greatly increase power dissipation. TMR may be pulled low to turn the converter off when the internal error amplifier is used. The error amplifier will source current when COMP is pulled below its saturated low voltage due to the nature of the class AB amplifier stage.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 TMR controls softstart, overload time-out, and automatic restart on overload, which is referred to as a hiccup function. VBIAS – This 5-V bias supply powers the bulk of the converter functions. VBIAS can be used to power the feedback optocoupler in isolated applications. External loading should be minimized to avoid excessive power dissipation. VBIAS has a UVLO function that inhibits converter operation at outputs of less than 4.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 TYPICAL CHARACTERISTICS VBIAS vs LOAD CURRENT VBIAS CURRENT LIMIT vs JUNCTION TEMPERATURE 5.3 19 5.25 18 5.1 15 14 13 TJ = -40oC 10 9.8 5.05 12 o TJ = -40 C 5 9.6 11 10 -40 4.95 1 TJ = 25oC 10.2 16 Voltage - V Current - mA TJ = 25oC 0 TJ = 125oC 17 5.2 VBIAS - V 10.6 10.4 o TJ = 125 C 5.15 AUX VOLTAGE vs LOAD CURRENT 3 2 5 4 -20 0 20 40 60 80 9.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 TYPICAL CHARACTERISTICS (continued) CONVERTER CURRENT LIMIT THRESHOLD (VRSP) vs JUNCTION TEMPERATURE TMR SOURCE/SINK CURRENT RATIO vs JUNCTION TEMPERATURE 10.08 504 10.04 10.02 10.00 9.98 9.96 9.94 9.92 9.90 -40 -20 0 20 40 60 80 5.0 4.8 503 4.6 502 4.4 Current - mA Current Limit Threshold - V Source/Sink Ratio 10.06 501 500 498 3.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 TYPICAL CHARACTERISTICS (continued) (VDD + RTN + SENP) DETECTION CURRENT vs SUPPLY VOLTAGE PoE CURRENT LIMIT vs JUNCTION TEMPERATURE 6 49.50 452 During PoE Detection 450 5 o Max Duty Cycle - % 448 o TJ = 125 C 446 4 IRTN - mA Current - mA MAXIMUM DUTY CYCLE vs OSCILLATOR FREQUENCY o TJ = 25 C 3 2 444 442 440 438 TJ = -40oC TJ = 25 C 49.25 TJ = 125oC 49.00 TJ = -40oC 48.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 APPLICATION INFORMATION PoE OVERVIEW The following text is intended as an aid in understanding the operation of the TPS23750 but not as a substitute for the actual IEEE 802.3af standard. Standards change and should always be referenced when making design decisions. The IEEE 802.3af specification defines a method of safely powering a PD over a cable, and then removing power if a PD is disconnected.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 PoE THRESHOLDS The TPS23750 has a number of internal comparators with hysteresis for stable switching between the various states as shown in Figure 29. Figure 30 relates the parameters in the Electrical Characteristics section to the PoE states. The mode labeled idle between classification and operation implies that the DET, CLASS, and RTN pins are all high impedance. PD Powered Idle Classification Detection VCL_H 1.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 The value of RCLASS should be chosen from the values listed in Table 2 based on the average power requirements of the PD. The power rating of this resistor should be chosen so that it is not overstressed for the required 75 ms classification period, during which 10 V is applied.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 PoE STARTUP EXAMPLE Figure 31 demonstrates detection, classification, and startup. The PSE controls the voltage on the PI, while the PD controls the current. The waveforms presented are the PI voltage, PI current, and dc/dc converter output voltage. Testing with different PSEs may result in waveforms that are not exactly the same because the IEEE 802.3af standard allows for different implementations. The first event is detection.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 COMP is also the input to the current-mode PWM section. A 1/5 divider scales the COMP input to the current comparators. Offsets built into the comparator assure that the duty cycle can be driven to 0%. The current limit comparator threshold of 0.5 V on the RSP pin provides a regulated current limit. The fault comparator detects a runaway condition when the peak voltage on RSP is greater than 0.75 V.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 Isolated PD converters that use an optocoupler, such as TL431-based circuits, should use the configuration of Figure 33. The MODE connection disables the internal error amplifier, rendering its output high impedance. A primary-side PWM softstart is internally implemented when the error amplifier is disabled. The same gain of 0.2 V/V appears before the PWM comparator.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 be used at voltages above VDD, but within their recommended voltage range with respect to VSS. SENP draws about 22.5 µA of current, while the SEN pin draws less than 1 µA. The SENP current can cause a small offset in the output voltage if connected to the center tap of an output voltage divider. If necessary, the offset can be minimized or compensated.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 Bias Supplies The TPS23750 has two bias supplies, the AUX input/output and the VBIAS supply, each with its own UVLO. The AUX supply is a current-limited, 10 V regulator that draws its current from VDD. It may be overridden by feeding a higher external voltage into this pin to improve efficiency. The gate driver draws large current pulses from this rail.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 CONVERTER STARTUP An imbalance between converter output capacitance, converter current limit, input bulk capacitance, and softstart time causes the converter to hiccup when attempting to start. The converter has a hard input current limit enforced by either the internal hotswap MOSFET or the PSE. If this current is exceeded, the converter meets its energy demands by drawing down the voltage on the bulk capacitor.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 5V Buck Converter 5V Flyback Converter V V OUT V V TMR TMR Successful Restart V COMP I LOAD OUT V COMP Fault Removed Fault Applied Fault Applied Secondary Softstart Successful Restart Fault Removed I LOAD Figure 36. TMR Pin Operation AUXILIARY SUPPLY ORing Many PoE-capable devices are designed to operate from either a wall adapter or PoE power.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 Option 1 inserts power before the TPS23750. A 48-V adapter that meets the TPS23750 UVLO is needed. If the adapter supply applies power to the PD before the PSE, it prevents the PSE from detecting the PD. This occurs because the input bridges are reverse biased and the Ethernet power path looks open. If the PSE is already powering the PD when the auxiliary source is plugged in, priority is given to the higher supply voltage.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 PoE Input Capacitor IEEE 802.3af requires a PD input capacitance between 0.05 µF and 0.12 µF during detection. This capacitor should be located directly adjacent to the TPS23750 as shown in Figure 1. A 100 V, 10%, X7R ceramic capacitor meets the specification over a wide temperature range. Input Transient Voltage Suppressor (TVS) A TVS across the rectified PoE voltage per Figure 1 must be used.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 Four major contributors to internal heat dissipation are the internal (hotswap) MOSFET I2R, the gate drive load, the internal bias power, and the optocoupler load. These four contributors form a template for the loss approximations of the common configurations shown in Table 3 . The total loss under low, medium, and high input voltages should be checked.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 P IN +5V DD + P+ ƪǒ V 1.5 Ań0.85 + 8.82 W (44 V * 2 Ǔ 8.82 W 37.84 V 0.75 V) ) Ǹ(44 V * 2 2 2 ƫ 1 W ) [37.84 V TJ + 65oC ) ǒ0.213 W 2 0.75 V) * 4 8.82 W 200 kHz] ) [37.84 V 10 nC 20 W + 37.84 V 2.2 mA] + 0.213 W 45oCńWǓ + 74.6 oC Table 4. Temperature Rise Calculator Summary VPSE RLOOP (Ω) VDD (V) P (W) TJ (°C) 44 20 37.84 0.213 74.6 50.5 10 47.13 0.233 75.5 57 0 55.5 0.258 76.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 CONCEPT SCHEMATICS The TPS23750 will work with almost any conventional circuit. Figure 38, Figure 39, and Figure 40 demonstrate the TPS23750’s use. Figure 38 is an isolated synchronous flyback, Figure 39 is a non-isolated flyback, and Figure 40 is a buck converter variant. Each of these circuits provides a single output.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 Buck Converter Example Figure 40 illustrates a particular form of buck converter where the output is derived with respect to the positive input rail. The application circuits are connected across the output, shown on J4, with terminal 2 as the application circuit ground reference.
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TPS23750 TPS23770 www.ti.com + + + SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 Figure 38.
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TPS23750 TPS23770 www.ti.com SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 Figure 39.
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TPS23750 TPS23770 www.ti.com + + SLVS590B – JULY 2005 – REVISED FEBRUARY 2008 Figure 40.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS23770PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 20 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 7.1 1.6 8.0 W Pin1 (mm) Quadrant 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS23770PWPR HTSSOP PWP 20 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.