Datasheet

TPS2363
www.ti.com SLUS680B –JANUARY 2006–REVISED JANUARY 2010
Table 9. STAT A (04h), STAT B (05h): Default 00h
FAULTA/B MAINA/B AUXA/B VAUXFA/B RSVD 12VFA/B RSVD 3VFA/B
R R R R/W R R/W R R/W
Valid write commands: The write commands are used to clear the faults in these registers.
• 00h, 01h, 04h, 05h, 10h, 11h, 14h, 15h
Valid read commands: 0Y through fY (Y corresponds to 0, 1, 4, or 5)
FAULT A/B : This bit indicates the status of the FAULTA/B pin.
• 1 – FAULTA/B pin is low.
• 0 – FAULTA/B pin is high (open drain).
When the bit has been set due to an over current, the corresponding enable bits or pins need to be cycled off
and back on to clear the fault and an echo reset in SMBus mode.
When FORCEONA/B is low, the FAULTA/B pin is in open drain state. FAULTA/B bit is not affected. When using
SMBUS for control, this bit is deactivated.
MAINA/B: This bit indicates the internal enable status of the main supplies.
• 1 – 3.3 V and 12 V are enabled (after ensuring there are no fault, UVLO, or FORCE conditions).
• 0 – 3.3 V and 12 V are disabled.
AUXA/B: This bit indicates the internal enable status of the AUX supply.
• 1 – 3.3 V AUX is enabled.
• 0 – 3.3 V AUX is disabled.
VAUXFA/B: This bit indicates and over current fault condition on VAUXA/B.
• 1 – There is an over current condition on VAUXA/B i.e.,
– Normal over current and timeout or
– Normal over current and TSHUT1
• 0 – No over current condition.
When TPS2363 is enabled using SMBus for control, this bit needs to be cleared by the master – ECHO RESET
condition. i.e., a “1” is written into this bit by the master. Once this is done, pin INT will be de-asserted (i.e. it
goes high).
12VFA/B : This bit indicates an over current fault condition on 12 V out – A
• 1 – There is an over current condition on 12 V out A ie.,
– Normal over current and timeout or
– Normal over current and TSHUT1 or
– Fast trip.
• 0 – No over current condition.
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Link(s): TPS2363