Datasheet

A6
A5 A4 A3 A2 A1 A0
R/W
D7 D6 D5 D4 D3 D2 D1 D0
1 19 9
SCL
SDA
Frame 1 SMBus Slave Address Byte
Frame 2 Data Byte from TPS2363
Start by
Master
ACK by
TPS2363
NACK by
MASTER
SMBUS Receive byte timing
TPS2363
www.ti.com SLUS680B –JANUARY 2006–REVISED JANUARY 2010
Figure 14. SMBus Receive Byte Timing
Table 7. Register Set
(1) (2) (3) (4)
TARGET REGISTER COMMAND BYTE VALUE POWER-ON DEFAULT
LABEL DESCRIPTION READ WRITE
Reserved 00h N/A N/A N/A
Reserved 01h N/A N/A N/A
CNTRLA Slot A control 02h 02h 00h
CNTRLB Slot B control 03h 03h 00h
STATA Slot A status 04h 04h 00h
STATB Slot B status 05h 05h 00h
Chip STAT Common status 06h 06h 00h
FUNCTION Special functions 07h 07h 0dh
(1) DMC = direct mode control.
(2) SMC = SMBus control.
(3) UVLO = Under Voltage Lockout.
(4) RSVD bits are read only and reads zero.
Table 8. Control Registers (02h, 03h)
(1)
-FORCEON
AUX PG(A/B) MAIN PG(A/B) RSVD RSVD RSVD MAINEN(A/B) AUXEN (A/B)
INHIB(A/B)
R R R R R R/W R/W R/W
(1) CNTRL A (02h), CNTRL B (03h): Default 00h (Do not write to this register in direct mode)
Valid write commands:
• 00h – Force mode is enabled with all supplies disabled.
• 01h – Enable VAUXA/B supply with force mode.
• 02h – Enable main supplies with force mode.
• 03h – Enable main and VAUXA/B with force mode.
• 04h – Disable FORCEON pins with all supplies disabled.
• 05h – Enable VAUXA/B supply without force mode.
• 06h – Enable main supplies without force mode.
• 07h – Enable all supplies without force mode.
(A write to this register in direct mode switchs the TPS2363 to SMBus mode, it will not switch back until power is
cycled on the TPS2363.)
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