Datasheet

SCL Period
Data holdData set up Data holdData set up
SCL
SDA
SMBus clock to data timing
A6
A5 A4 A3 A2 A1 A0 R/W
R7 R6 R5 R4 R3 R2 R1 R0
D7 D6 D5 D4 D3 D2 D1 D0
1 1
1
9 9
9
SCL
SDA
SMBus Timing Diagram for a write operation
Frame1 SMBus Slave Address Byte
Frame2 Address Pointer Register Byte
Frame 3 Data Byte
Start by
Master
ACK by
TPS2363
ACK by
TPS2363
ACK by
TPS2363
A6
A5 A4 A3 A2 A1 A0 R/W
R7 R6 R5 R4 R3 R2 R1 R0
1 19 9
SCL
SDA
SMBus Timing Diagram for a read operation
Frame1 SMBus Slave Address Byte
Frame2 Address Pointer Register Byte
Start by
Master
ACK by
TPS2363
ACK by
TPS2363
A6
A5 A4 A3 A2 A1 A0
R/W
D7 D6 D5 D4 D3 D2 D1 D0
1 19 9
SCL
(
Continued
)
SDA
(
Continued
)
Frame3 SMBus Slave Address Byte
Frame 4 Data Byte from TPS2363
Start by
Master
ACK by
TPS2363
NACK by
MASTER
SCL
( Continued
)
SDA
(
Continued
)
TPS2363
SLUS680B –JANUARY 2006–REVISED JANUARY 2010 www.ti.com
Echo Reset
Some bits in the STATA/B and the common status register are fault indications that can cause an interrupt.
These bits remain set even if the fault condition has been cleared. This is done to allow time for the controller to
process the interrupt and read the fault condition. When the controller writes a 1 back to the set bit, the bit is
cleared on the next read of the register if the fault condition has been removed. This is called echo reset. These
bits are STATA/B positions D0, D2, D4, and common status register D1 and D2.
Figure 12. SMBus Clock to Data Timing
Figure 13. SMBus Timing Diagram for Write/Read Operation
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