Datasheet

5.63
3
+ 1.88 A
dv
dt
+
I
GATE
C
MILLER
(
gfs ) 1
)
I
LOAD
C
LOAD
+
I
GATE
ǒ
C
MILLER
4
Ǔ
ǒ
C
MILLER
4
Ǔ
+
I
GATE
C
LOAD
I
LOAD
C
MILLER
+
(
25 mA 2000 mF
)
1.88 4
+ 6.6 nF,
(
use 6800 pF
)
TPS2363
SLUS680B –JANUARY 2006–REVISED JANUARY 2010 www.ti.com
For the 12-V output, a P-channel FET is used in order to get sufficient V
GS
for control. In this configuration the
FET is a high-gain amplifier. The slew rate for the 12 V is controlled by a Miller capacitance from the gate of the
FET to the source. The calculation is the same as the 3.3 V case but C
MILLER
is reduced because by the gfs of
the FET.
Example:
• The PCIExpress specification allows for 2000 mF maximum capacitance for the 12 V.
• Minimum trip point for the 12 V with an 8 mΩ is 5.63 A. Use .
• Assume a gfs for the FET of about 3.
• I
GATE
= 25 mA .
The equation to calculate the slew rate of the 12 V is:
The delay time from ONA/B is controlled by the sum C
GATE
and C
MILLER
. Add a gate capacitor to the 12-V FET
gate to keep the power on delay about the same as the 3.3-V FET. Since C
MILLER
is small compared to the 3.3-V
C
GATE
, use the same capacitor value for 12-V gate as for the 3.3 V.
The table below shows the recommended gate capacitor for the 3.3-V and 12-V supply for the different connector
widths.
Table 6. Recommended Gate Capacitor
(1)
VOLTAGE WIDTH C
MILLER
(pF) C
GATE
(nF)
+3.3 All 22
+12 All 6800 22
(1) Recommended capacitors to limit inrush current.
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