Datasheet
I
LOAD
+ C
LOAD
dv
dt
,
dv
dt
+
I
LOAD
C
LOAD
I
GATE
+ C
GATE
dv
dt
,
dv
dt
+
I
GATE
C
GATE
I
LOAD
C
LOAD
+
I
GATE
C
GATE
C
GATE
+
ǒ
I
GATE
I
LOAD
Ǔ
C
LOAD
+
ǒ
25 mA
1.15 A
Ǔ
1000 mF + 21.7 nF
(
use 22 mF
)
dv
dt
25 mA
22 nF
+ 1136 Vńs
3.3
1136 Vńs
+ 2.9 ms
TPS2363
www.ti.com
SLUS680B –JANUARY 2006–REVISED JANUARY 2010
Inrush Current
Inrush current is the large current at start-up due to capacitive loads. It can reduce the system voltage causing
problems for other operating modules in the system. High inrush currents can destroy connector pins and circuit
board etch. With over-current circuit breaker controls like the TPS2363, inrush current can turn on the
over-current comparator and prevent the slot from turning on unless the proper gate capacitors and fault time is
selected.
Inrush current can be limited by controlling the turn on rate of the power to the slot. Average inrush current can
be calculated knowing the load capacitance and the turn on time of the slot voltage. In the usual case, the slot
controller will not trip if the average inrush is less than one-third the over-current set point of the slot controller.
For the 3.3-V output an N-channel FET is used in a source follower configuration. The slot voltage turn on can be
slowed by connecting a capacitor to the FET gate increasing the turn on time of the output. To determine the
gate capacitor value, calculate the dv/dt for the load and then apply the same dv/dt to the FET gate. The
following example shows how to calculate the gate capacitor value for the 3.3-V main power.
Example:
• The PCIExpress specification allows for 1000-mF maximum capacitance for the 3.3 V.
• Minimum trip point for the 3.3 V with 13 mΩ is 3.46 A. Use 3.46 / 3 = 1.15 A.
• I
GATE
= 25 mA
The 3.3-V slew rate is
From ONA/B asserted, the output doesn’t turn on until the gate voltage rises to V
GS(th)
. The gate capacitor
causes a slight delay of the voltage ramp start from the power signal asserted.
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