Datasheet

TPS2359
SLUS792H –FEBRUARY 2008–REVISED MAY 2013 www.ti.com
Register 5
Table 8. Register 5: Channel 3B Configuration (Read/Write)
BIT NAME DEFAULT DESCRIPTION
0 3BFT0 1 Setting bit increases 3B fault time by 0.45 ms.
1 3BFT1 0 Setting bit increases 3B fault time by 0.9 ms.
2 3BFT2 0 Setting bit increases 3B fault time by 1.8 ms.
3 3BFT3 0 Setting bit increases 3B fault time by 3.6 ms.
4 3BFT4 0 Setting bit increases 3B fault time by 7.2 ms.
5 3BEN 0 Clearing bit disables 3B.
6 3BUV 0 Setting bit prevents enabling unless OUT3B < bleed down threshold.
7 3BDS 0 Clearing bit disconnects OUT3B bleed down resistor.
3BFT[4:0] These five bits adjust the 3B channel fault time. The least-significant bit has a nominal weight of 0.45
ms, so fault times ranging from 0.45 ms (for code 00001B) to 13.95 ms (for code 11111B) can be programmed.
The code xFT = 00000B should not be used. In general the shortest fault time that fully charges downstream
bulk capacitors without generating a fault should be used. See Setting Fault Time section.
3BEN This bit serves as a master enable for channel 3B. Setting this bit allows the 3B channel to operate
normally, provided the EN3B pin is also asserted. Clearing this bit disables the channel by removing gate drive to
the internal pass FET, regardless of the state of the EN3B pin.
3BUV Setting this bit prevents channel 3B from turning on until OUT3B falls below the bleed down threshold of
100 mV. This feature ensures that downstream devices reset by requiring their supply voltage to fall to nearly
zero before the channel can enable them.
3BDS Clearing this bit disconnects the bleed down resistor that otherwise connects from OUT3B to ground.
Systems using redundant power supplies should clear 3BDS to prevent the bleed down resistor from
continuously sinking current.
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