Datasheet

TPS2359

www.ti.com

SLUS792H –FEBRUARY 2008–REVISED MAY 2013

Table 7. Register 4: Channel 12B Configuration (Read/Write)

BIT NAME DEFAULT DESCRIPTION

0 12BFT0 1 Setting bit increases 12B fault time by 0.45 ms.

1 12BFT1 0 Setting bit increases 12B fault time by 0.9 ms.

2 12BFT2 0 Setting bit increases 12B fault time by 1.8 ms.

3 12BFT3 0 Setting bit increases 12B fault time by 3.6 ms.

4 12BFT4 0 Setting bit increases 12B fault time by 7.2 ms.

5 12BEN 0 Clearing bit disables 12B by pulling PASSB and BLKB to 0 V.

6 12BUV 0 Setting bit prevents enabling unless OUT12B < bleed down threshold.

7 12BDS 0 Clearing bit disconnects OUT12B bleed down resistor.

12BFT[4:0] These five bits adjust the 12B channel fault time. The least-significant bit has a nominal weight of

0.45 ms, so fault times ranging from 0.45 ms (for code 00001B) to 13.95 ms (for code 11111B) can be

programmed. The code xFT = 00000B should not be used. In general the shortest fault time that fully charges

downstream bulk capacitors without generating a fault should be used. Once the load capacitors have fully

charged, the fault time can be reduced to provide faster short circuit protection. See Setting Fault Time section.

12BEN This bit serves as a master enable for channel 12B. Setting this bit allows the 12B channel to operate

normally. Clearing this bit disables the channel by pulling PASSB and BLKB low.

12BUV Setting this bit prevents channel 12B from turning on until OUT12B falls below the bleed down threshold

of 100 mV. This feature ensures that downstream devices reset by requiring their supply voltage to fall to nearly

zero before the channel can enable them.

12BDS Clearing this bit disconnects the bleed down resistor that otherwise connects from OUT12B to ground.

Systems using redundant power supplies should clear 12BDS to prevent the bleed down resistor from

continuously sinking current.

Product Folder Links: TPS2359