Datasheet

TPS2359

SLUS792H –FEBRUARY 2008–REVISED MAY 2013

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Table 4. Register 1: Channel 12A Configuration (Read/Write)

BIT NAME DEFAULT DESCRIPTION

0 12AFT0 1 Setting bit increases 12A fault time by 0.45 ms.

1 12AFT1 0 Setting bit increases 12A fault time by 0.9 ms.

2 12AFT2 0 Setting bit increases 12A fault time by 1.8 ms.

3 12AFT3 0 Setting bit increases 12A fault time by 3.6 ms.

4 12AFT4 0 Setting bit increases 12A fault time by 7.2 ms.

5 12AEN 0 Clearing bit disables 12A by pulling PASSA and BLKA to 0 V.

6 12AUV 0 Setting bit prevents enabling unless OUT12A < bleed down threshold.

7 12ADS 0 Clearing bit disconnects OUT12A bleed down resistor.

12AFT[4:0] These five bits adjust the 12A channel fault time. The least-significant bit has a nominal weight of

0.45 ms, so fault times ranging from 0.45 ms (for code 00001B) to 13.95 ms (for code 11111B) can be

programmed. The code xFT = 00000B should not be used. In general the shortest fault time that fully charges

downstream bulk capacitors without generating a fault should be used. Once the load capacitors have fully

charged, the fault time can be reduced to provide faster short circuit protection. See Setting Fault Time section.

12AEN This bit serves as a master enable for channel 12A. Setting this bit allows the 12A channel to operate

normally. Clearing this bit disables the channel by pulling PASSA and BLKA low.

12AUV Setting this bit prevents channel 12A from turning on until OUT12A falls below the bleed down threshold

of 100 mV. This feature ensures that downstream devices reset by requiring their supply voltage to fall to nearly

zero before the channel can enable them.

12ADS Clearing this bit disconnects the bleed down resistor that otherwise connects from OUT12A to ground.

Systems using redundant power supplies should clear 12ADS to prevent the bleed down resistor from

continuously sinking current.

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