Datasheet

TPS2359
www.ti.com SLUS792H –FEBRUARY 2008–REVISED MAY 2013
Summary of Registers
Table 2. Summary of Registers
BIT NAME DEFAULT DESCRIPTION
Register 0 Read/Write channel 12A configuration
0 12ACL0 1 Clearing bit reduces 12A current limit and fast threshold by 5%.
1 12ACL1 1 Clearing bit reduces 12A current limit and fast threshold by 10%.
2 12ACL2 1 Clearing bit reduces 12A current limit and fast threshold by 20%.
3 12ACL3 1 Clearing bit reduces 12A current limit and fast threshold by 40%.
4 12APG0 1 Clearing bit reduces 12A power good threshold by 600mV.
5 12APG1 1 Clearing bit reduces 12A power good threshold by 1.2 V.
6 12AHP 0 Setting bit shifts 12A OR VTURNOFF from –3 mV to +3 mV nominal.
7 12AOR 1 Clearing bit turns off 12A ORing FET by pulling BLKA low.
Register 1 Read/Write channel 12A configuration
0 12AFT0 1 Setting bit increases 12A fault time by 0.45 ms.
1 12AFT1 0 Setting bit increases 12A fault time by 0.9 ms.
2 12AFT2 0 Setting bit increases 12A fault time by 1.8 ms.
3 12AFT3 0 Setting bit increases 12A fault time by 3.6 ms.
4 12AFT4 0 Setting bit increases 12A fault time by 7.2 ms.
5 12AEN 0 Clearing bit disables 12A by pulling PASSA and BLKA to 0 V.
6 12AUV 0 Setting bit prevents enabling unless OUT12A < bleed down threshold.
7 12ADS 0 Clearing bit disconnects OUT12A bleed down resistor.
Register 2 Read/Write channel 3A configuration
0 3AFT0 1 Setting bit increases 3A fault time by 0.45 ms.
1 3AFT1 0 Setting bit increases 3A fault time by 0.9 ms.
2 3AFT2 0 Setting bit increases 3A fault time by 1.8 ms.
3 3AFT3 0 Setting bit increases 3A fault time by 3.6 ms.
4 3AFT4 0 Setting bit increases 3A fault time by 7.2 ms.
5 3AEN 0 Clearing bit disables 3A.
6 3AUV 0 Setting bit prevents enabling unless OUT3A < bleed down threshold.
7 3ADS 0 Clearing bit disconnects OUT3A bleed down resistor.
Register 3 Read/Write channel 12B configuration
0 12BCL0 1 Clearing bit reduces 12B current limit and fast threshold by 5%.
1 12BCL1 1 Clearing bit reduces 12B current limit and fast threshold by 10%.
2 12BCL2 1 Clearing bit reduces 12B current limit and fast threshold by 20%.
3 12BCL3 1 Clearing bit reduces 12B current limit and fast threshold by 40%.
4 12BPG0 1 Clearing bit reduces 12B power good threshold by 600 mV.
5 12BPG1 1 Clearing bit reduces 12B power good threshold by 1.2 V.
6 12BHP 0 Setting bit shifts 12B OR VTURNOFF from –3 mV to +3 mV nominal.
7 12BOR 1 Clearing bit turns off 12B ORing FET by pulling BLKB low.
Register 4 Read/Write channel 12B configuration
0 12BFT0 1 Setting bit increases 12B fault time by 0.45 ms.
1 12BFT1 0 Setting bit increases 12B fault time by 0.9 ms.
2 12BFT2 0 Setting bit increases 12B fault time by 1.8 ms.
3 12BFT3 0 Setting bit increases 12B fault time by 3.6 ms.
4 12BFT4 0 Setting bit increases 12B fault time by 7.2 ms.
5 12BEN 0 Clearing bit disables 12B by pulling PASSB and BLKB to 0 V.
6 12BUV 0 Setting bit prevents enabling unless OUT12B < bleed down threshold.
7 12BDS 0 Clearing bit disconnects OUT12B bleed down resistor.
Register 5 Read/Write channel 3B configuration
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