Datasheet

R
VSENSE_TOP
+
V
O_min
* 1.225
1.225
R
VSENSE_BOT
I
LMT
+
R
ISET
50 10
–6
R
ISENSE
TPS2330
TPS2331
SLVS277G –MARCH 2000–REVISED JULY 2013 www.ti.com
pin. Once the gate has been pulled below approximately 1.5 V, this driver is disengaged and the UVLO driver
is enabled instead.
SETTING THE CURRENT-LIMIT CIRCUIT-BREAKER THRESHOLD
The current sensing resistor R
ISENSE
and the current limit setting resistor R
ISET
determine the current limit of the
channel, and can be calculated by the following equation:
(2)
Typically R
ISENSE
is usually very small (0.001 Ω to 0.1 Ω). If the trace and solder-junction resistances between the
junction of R
ISENSE
and ISENSE and the junction of R
ISENSE
and R
ISET
are greater than 10% of the R
ISENSE
value,
then these resistance values should be added to the R
ISENSE
value used in the foregoing calculation.
Table 4 shows some of the current-sense resistors available in the market.
Table 4. Some Current-Sense Resistors
CURRENT RANGE
PART NUMBER DESCRIPTION MANUFACTURER
(A)
0 to 1 WSL-1206, 0.05 1% 0.05 Ω, 0.25 W, 1% resistor
1 to 2 WSL-1206, 0.025 1% 0.025 Ω, 0.25 W, 1% resistor
2 to 4 WSL-1206, 0.015 1% 0.015 Ω, 0.25 W, 1% resistor
Vishay Dale
4 to 6 WSL-2010, 0.010 1% 0.010 Ω, 0.5 W, 1% resistor
6 to 8 WSL-2010, 0.007 1% 0.007 Ω, 0.5 W, 1% resistor
8 to 10 WSR-2, 0.005 1% 0.005 Ω, 0.5 W, 1% resistor
SETTING THE POWER-GOOD THRESHOLD VOLTAGE
The two feedback resistors R
VSENSE_TOP
and R
VSENSE_BOT
connected between V
O
and ground form a resistor
divider, setting the voltage at the VSENSE pins. VSENSE voltage equals:
V
I(SENSE)
= V
O
× R
VSENSE_BOT
/(R
VSENSE_TOP
+ R
VSENSE_BOT
)
This voltage is compared to an internal voltage reference (1.225 V ±2%) to determine whether the output voltage
level is within a specified tolerance. For example, given a nominal output voltage at V
O
, and defining V
O_min
as
the minimum required output voltage, then the feedback resistors are defined by:
(3)
Start the process by selecting a large standard resistor value for R
VSENSE_BOT
to reduce power loss. Then
R
VSENSE_TOP
can be calculated by inserting all of the known values into the preceding equation. When V
O
is lower
than V
O_min
, PWRGD is low as long as the controller is enabled.
UNDERVOLTAGE LOCKOUT (UVLO)
The TPS2330/TPS2331 includes an undervoltage lockout (UVLO) feature that monitors the voltage present on
the VREG pin. This feature disables the external MOSFET if the voltage on VREG drops below 2.78 V (nominal)
and re-enables normal operation when it rises above 2.85 V (nominal). Because VREG is fed from IN through a
low-dropout voltage regulator, the voltage on VREG tracks the voltage on IN within 50 mV. While the
undervoltage lockout is engaged, GATE is held low by an internal PMOS pulldown transistor, ensuring that the
external MOSFET transistor remain off at the times, even if the power supply has fallen to 0 V.
POWER-UP CONTROL
The TPS2330/TPS2331 includes a 500-μs (nominal) start-up delay that ensures that internal circuitry has
sufficient time to start before the device begins turning on the external MOSFETs. This delay is triggered only on
the rapid application of power to the circuit. If the power supply ramps up slowly, the undervoltage lockout
circuitry provides adequate protection against undervoltage operation.
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