Datasheet

TPS22941, TPS22942, TPS22943, TPS22944, TPS22945
SLVS832C –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com
Output Capacitor
A 0.1-μF capacitor, C
OUT
, should be placed between V
OUT
and GND. This capacitor will prevent parasitic board
inductances from forcing V
OUT
below GND when the switch turns off. For the TPS2294x, the total output
capacitance needs to be kept below a maximum value, C
OUT(max)
, to prevent the part from registering an
over-current condition and turning-off the switch. The maximum output capacitance can be determined from the
following formula, C
OUT
= I
LIM
(MAX) x t
BLANK
(MIN) ÷ V
IN
Due to the integral body diode in the PMOS switch, a C
IN
greater than C
OUT
is highly recommended. A C
OUT
greater than C
IN
can cause V
OUT
to exceed V
IN
when the system supply is removed. This could result in current
flow through the body diode from V
OUT
to V
IN
.
Power Dissipation
During normal operation as a switch, the power dissipation is small and has little effect on the operating
temperature of the part. The parts with the higher current limits will dissipate the most power and that will only
be,
P = (I
LIM
)
2
× r
ON
= (0.2)
2
× 0.4 = 16 mW when V
IN
= 5.5 V
If the part goes into current limit the maximum power dissipation will occur when the output is shorted to ground.
For TPS22941/2/5, the power dissipation scales by the auto-restart time (t
RESTART
) and the overcurrent blanking
time (t
BLANK
) so that the maximum power dissipated is:
P(max) = (t
BLANK
÷ (t
RESTART
+ t
BLANK
)) × (V
IN
(max)) × I
LIM
(max) = (10 ÷ (80 + 10) × 5.5 × 0.2 = 122 mW
When using the TPS22943 and TPS22944, a short on the output causes the part to operate in a constant current
state, dissipating a worst-case power as calculated above until the thermal shutdown activates. It then cycles in
and out of thermal shutdown so long as the ON pin is active and the short is present.
Board Layout
For best performance, all traces should be as short as possible. To be most effective, the input and output
capacitors should be placed close to the device to minimize the effects that parasitic trace inductances may have
on normal and short-circuit operation. Using wide traces for V
IN
, V
OUT
, and GND will help minimize parasitic
electrical effects along with minimizing the case to ambient thermal impedance.
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Product Folder Link(s): TPS22941 TPS22942 TPS22943 TPS22944 TPS22945