Datasheet

Laser Marking View
Bump View
C
B
2 1
A
C
B
1 2
A
TPS22924C
SLVSA52C NOVEMBER 2009REVISED JUNE 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
T
A
PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(3)
TPS22924CYZPR (without back
–40°C to 85°C DSBGA – YZP (0.5-mm pitch) Reel _ _ _ 5L _
side coating)
TPS22924CYZPRB (with back
–40°C to 85°C DSBGA – YZP (0.5-mm pitch) Reel _ _ _ 5L _
side coating)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to
designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
YZP PACKAGE
TERMINALS ASSIGNMENTS (YZP PACKAGE)
C GND ON
B VOUT VIN
A VOUT VIN
1 2
TERMINAL FUNCTIONS
NO. NAME DESCRIPTION
C1 GND Ground
C2 ON Switch control input, active high. Do not leave floating
A1, B1 VOUT Switch output
A2, B2 VIN Switch input, bypass this input with a ceramic capacitor to ground
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Product Folder Links: TPS22924C