Datasheet

TPS22920
www.ti.com
SLVSAY8A JUNE 2011REVISED JULY 2013
APPLICATION INFORMATION
ON/OFF CONTROL
The ON pin controls the state of the switch. Asserting ON high enables the switch. ON is active high and has a
low threshold, making it capable of interfacing with low-voltage signals. The ON pin is compatible with standard
GPIO logic threshold. It can be used with any microcontroller with 1.2-V, 1.8-V, 2.5-V or 3.3-V GPIOs.
INPUT CAPACITOR
To limit the voltage drop on the input supply caused by transient inrush currents when the switch turns on into a
discharged load capacitor or short-circuit, a capacitor needs to be placed between V
IN
and GND. A 1-μF ceramic
capacitor, C
IN
, placed close to the pins is usually sufficient. Higher values of C
IN
can be used to further reduce
the voltage drop.
OUTPUT CAPACITOR
Due to the integral body diode in the NMOS switch, a C
IN
greater than C
L
is highly recommended. A C
L
greater
than C
IN
can cause V
OUT
to exceed VIN when the system supply is removed. This could result in current flow
through the body diode from V
OUT
to V
IN
. A C
IN
to C
L
ratio of 10 to 1 is recommended for minimizing V
IN
dip
caused by inrush currents during startup.
OUTPUT PULL-DOWN
The output pulldown is active when the user is turning off the main pass FET. The pulldown discharges the
output rail to approximately 10% of the rail, and then the output pulldown is automatically disconnected to
optimize the shutdown current.
BOARD LAYOUT
For best performance, all traces should be as short as possible. To be most effective, the input and output
capacitors should be placed close to the device to minimize the effects that parasitic trace inductances may have
on normal operation. Using wide traces for V
IN
, V
OUT
, and GND helps minimize the parasitic electrical effects
along with minimizing the case to ambient thermal impedance.
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