Datasheet

J(MAX) A
D(MAX)
JA
T T
P
θ
-
=
A1
Gnd
Via
VIA to Power Ground Plane
V Bypass
Capacitor
IN
V Bypass
Capacitor
OUT
To GPIO
control
B2 B1
VOUT
A2
VIN
ON
GND
Gnd
Via
TPS22910A , TPS22912C , TPS22913B , TPS22913C
www.ti.com SLVSB49D –NOVEMBER 2011–REVISED MAY 2014
12 Power Supply Recommendations
The device is designed to operate with a VIN range of 1.4 V to 5.5 V.
13 Layout
13.1 Layout Guidelines
For best performance, all traces should be as short as possible. To be most effective, the input and output
capacitors should be placed close to the device to minimize the effects that parasitic trace inductances may have
on normal operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects
along with minimizing the case to ambient thermal impedance.
13.2 Layout Example
The figure below shows an example of a layout. Notice the thermal vias located under the exposed thermal pad
of the device. This allows for thermal diffusion away from the device.
13.3 Thermal Considerations
The maximum IC junction temperature should be restricted to 125° C under normal operating conditions. To
calculate the maximum allowable dissipation, P
D(max)
for a given output current and ambient temperature, use the
following equation as a guideline:
(5)
where
• P
D(max)
= maximum allowable power dissipation
• T
J(max)
= maximum allowable junction temperature
• T
A
= ambient temperature of the device
• Θ
JA
= junction to air thermal impedance. See the Thermal Information section. This parameter is highly
dependent upon board layout.
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