Datasheet
TPS22908
SLVSBI7B –JULY 2012–REVISED MAY 2013
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APPLICATION INFORMATION
ON/OFF CONTROL
The ON pin controls the state of the switch. Asserting ON high enables the switch. ON is active high and has a
low threshold making it capable of interfacing with low-voltage signals. The ON pin is compatible with standard
GPIO logic threshold. It can be used with any microcontroller with 1.2-V or higher GPIOs.
INPUT CAPACITOR (OPTIONAL)
To limit the voltage drop on the input supply caused by transient inrush currents when the switch turns on into a
discharged load capacitor or short-circuit, a capacitor can be placed between V
IN
and GND. A 1-µF ceramic
capacitor, C
IN
, placed close to the pins, is usually sufficient. Higher values of C
IN
can be used to further reduce
the voltage drop during high-current application. When switching heavy loads, it is recommended to have an
input capacitor about 10 times higher than the output capacitor to avoid excessive voltage drop.
OUTPUT CAPACITOR (OPTIONAL)
Due to the integrated body diode of the PMOS switch, a C
IN
greater than C
L
is highly recommended. A C
L
greater than C
IN
can cause V
OUT
to exceed V
IN
when the system supply is removed. This could result in current
flow through the body diode from V
OUT
to V
IN
. A C
IN
to C
L
ratio of at least 10 to 1 is recommended for minimizing
V
IN
dip caused by inrush currents during startup; however, a 10 to 1 ratio for capacitance is not required for
proper functionality of the device. A ratio smaller than 10 to 1 (such as 1 to 1) could cause slightly more V
IN
dip
at turn on due to inrush currents.
BOARD LAYOUT
For best performance, all traces should be as short as possible. To be most effective, the input and output
capacitors should be placed close to the device to minimize the effects that parasitic trace inductances may have
on normal operation. Using wide traces for V
IN
, V
OUT
, and GND helps minimize the parasitic electrical effects
along with minimizing the case to ambient thermal impedance.
Figure 32. Layout
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