Datasheet

  
   
   
SLVS317 − MAY 2001
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, T
J
= 25°C, V
I(5V)
= 5 V, V
I(3.3V)
= 3.3 V, V
I(12V)
= 12 V (not applicable for
TPS2223), all outputs unloaded (unless otherwise noted) (continued)
logic section (CLOCK, DATA, LATCH, RESET, SHDN, OC)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
I(/RESET)
(see Note 2)
RESET = 5.5 V −1 1
I
I(/RESET)
(see Note 2)
RESET = 0 V −30 −20 −10
I
I(/SHDN)
(see Note 2)
SHDN = 5.5 V −1 1
I
I
Input current, logic
I
I(/SHDN)
(see Note 2)
SHDN = 0 V −50 −3
µA
I
I
Input current, logic
I
I(LATCH)
(see Note 2)
LATCH = 5.5 V 50
µA
I
I(LATCH)
(see Note 2)
LATCH = 0 V −1 1
I
I(CLOCK, DATA)
0 V to 5.5 V −1 1
V
IH
High-level input voltage, logic 2 V
V
IL
Low-level input voltage, logic 0.8 V
V
O(sat)
Output saturation voltage at OC I
O
= 2 mA 0.14 0.4 V
I
lkg
Leakage current at OC V
O(/OC)
= 5.5 V 0 1 µA
NOTE 2: LATCH has low current pulldown. RESET and SHDN have low-current pullup.
UVLO and POR (power-on reset)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
I(3.3V)
Input voltage at 3.3V pin, UVLO 3.3 V level below which all switches are Hi-Z 2.4 2.7 2.9 V
V
hys(3.3V)
UVLO hysteresis voltage at VA
(see Note 1)
70 100 mV
V
I(5V)
Input voltage at 5V pin, UVLO 5 V level below which only 5V switches are Hi-Z 2.3 2.5 2.9 V
V
hys(5V)
UVLO hysteresis voltage at 5V
(see Note 1)
70 100 mV
t
df
Delay time for falling response, UVLO
(see Note 1)
Delay from voltage hit (step from 3 V to 2.3 V)
to Hi-Z control (90% V
G
to GND)
4 µs
V
I(POR)
Input voltage, power-on reset
(see Note 1)
3.3 V voltage below which POR is asserted
causing a RESET internally with all line
switches open and all discharge switches
closed.
1.7 V
NOTE 1: Specified by design; not tested in production.