Datasheet

  
   
   
SLVS317 − MAY 2001
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
logic inputs and outputs
The serial interface consists of DATA, CLOCK, and LATCH leads. The data is clocked in on the positive edge
of the clock (see Figure 2). The 11-bit (D0−D10) serial data word is loaded during the positive edge of the latch
signal. The positive edge of the latch signal should occur before the next positive edge of the clock occurs.
The serial interface of the device is compatible with serial-interface PCMCIA controllers.
An overcurrent output (OC
) is provided to indicate an overcurrent or overtemperature condition in any of the
xVCC and xVPP outputs as previously discussed.
TPS2223, TPS2224 and TPS2226 control logic
xVPP
AVPP CONTROL SIGNALS
OUTPUT
V_AVPP
BVPP CONTROL SIGNALS
OUTPUT
V_BVPP
D8 (SHDN) D0 D1 D9
OUTPUT
V_AVPP
D8 (SHDN) D4 D5 D10
OUTPUT
V_BVPP
1 0 0 X 0 V 1 0 0 X 0 V
1 0 1 0 3.3 V 1 0 1 0 3.3 V
1 0 1 1 5 V 1 0 1 1 5 V
1 1 0 X 12 V
†
1 1 0 X 12 V
†
1 1 1 X Hi-Z 1 1 1 X Hi-Z
0 X X X Hi-Z 0 X X X Hi-Z
†
The output V_xVPP is Hi-Z for TPS2223.
xVCC
AVCC CONTROL SIGNALS
OUTPUT
V_AVCC
BVCC CONTROL SIGNALS
OUTPUT
V_BVCC
D8 (SHDN) D3 D2
OUTPUT
V_AVCC
D8 (SHDN) D6 D7
OUTPUT
V_BVCC
1 0 0 0 V 1 0 0 0 V
1 0 1 3.3 V 1 0 1 3.3 V
1 1 0 5 V 1 1 0 5 V
1 1 1 0 V 1 1 1 0 V
0 X X Hi-Z 0 X X Hi-Z