Datasheet
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PARAMETER MEASUREMENT INFORMATION
50%
LATCH
V
DD
GND
10%
90%
t
pd(on)
GND
V
O(xVPP)
Propagation Delay (xVPP)
50%
LATCH
V
DD
GND
10%
90%
t
pd(on)
GND
V
O(xVCC)
Propagation Delay (xVCC)
10%
90%
t
r
GND
V
O(xVPP)
Rise/Fall Time (xVPP)
t
f
10%
90%
t
r
GND
V
O(xVCC)
Rise/Fall Time (xVCC)
t
f
50%
V
DD
GND
10%
90%
t
on
GND
V
O(xVCC)
Turnon/off Time (xVCC)
xVPP
VOLTAGE WAVEFORMS
LOAD CIRCUIT (xVPP)
I
O(xVPP)
xVCC
50%
LATCH
V
DD
GND
10%
90%
t
on
GND
V
O(xVPP)
Turnon/off Time (xVPP)
I
O(xVCC)
t
pd(off)
t
pd(off)
t
off
t
off
LOAD CIRCUIT (xVCC)
V
I(12V/5V/3.3V)
V
I(5V/3.3V)
V
I(12V/5V/3.3V)
V
I(5V/3.3V)
V
I(12V/5V/3.3V)
V
I(5V/3.3V)
LATCH
D10
D9
D8 D7
D6
D5
D4 D3
D2
DATA
LATCH
CLOCK
D1
D0
Data Setup Time Data Hold Time Latch Delay Time
Clock Delay Time
TPS2220A , TPS2223A
TPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
Figure 1. Test Circuits and Voltage Waveforms
NOTE: Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next
positive edge of the clock. For definition of D0 to D10, see the control logic table.
Figure 2. Serial-Interface Timing for TPS2226A
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Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A