Datasheet

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TPS2220A , TPS2223A
TPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
ELECTRICAL CHARACTERISTICS (continued)
T
J
= 25 ° C, V
I(5V)
= 5 V, V
I(3.3V)
= 3.3 V, V
I(12V)
= 12 V (not applicable for TPS2223A), all outputs unloaded (unless otherwise
noted)
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
LOGIC SECTION (CLOCK, DATA, LATCH, RESET, SHDN, OC)
RESET = 5.5 V -1 1
I
I(/RESET)
(5)
RESET = 0 V -30 -20 -10
SHDN = 5.5 V -1 1
I
I(/SHDN)
(5)
I
I
Input current, logic SHDN = 0 V -50 -3 µ A
LATCH = 5.5 V 50
I
I(LATCH)
(5)
LATCH = 0 V -1 1
I
I(CLOCK, DATA)
0 V to 5.5 V -1 1
V
IH
High-level input voltage, logic 2 V
V
IL
Low-level input voltage, logic 0.8 V
V
O(sat)
Output saturation voltage at OC I
O
= 2 mA 0.14 0.4 V
I
lkg
Leakage current at OC V
O(/OC)
= 5.5 V 0 1 µ A
UVLO AND POR (POWER-ON RESET)
V
I(3.3V)
Input voltage at 3.3V pin, UVLO 3.3-V level below which all switches are Hi-Z 2.4 2.7 2.9 V
V
hys(3.3V)
UVLO hysteresis voltage at VA
(6)
100 mV
V
I(5V)
Input voltage at 5V pin, UVLO 5-V level below which only 5V switches are Hi-Z 2.3 2.5 2.8 V
Delay from voltage hit (step from 3 V to 2.3 V) to
V
hys(5V)
UVLO hysteresis voltage at 5V
(6)
100 mV
Hi-Z control (90% V
G
to GND)
t
df
Delay time for falling response, UVLO
(6)
4 µ s
3.3-V voltage below which POR is asserted causing a
V
I(POR)
Input voltage, power-on reset
(6)
RESET internally with all line switches open and all 1.7 V
discharge switches closed.
(5) LATCH has low-current pulldown. RESET and SHDN have low-current pullup.
(6) Specified by design; not tested in production.
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Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A