Datasheet
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIONS
TPS2220A , TPS2223A
TPS2224A , TPS2226A
SLVS428E – MAY 2002 – REVISED MSRCH 2008
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
over operating free-air temperature range (unless otherwise noted)
(1)
TPA222xA UNIT
V
I(3.3V)
– 0.3 to 5.5 V
V
I
Input voltage range for card power V
I(5V)
– 0.3 to 5.5 V
V
I(12V)
(2)
– 0.3 to 14 V
Logic input/output voltage – 0.3 to 6 V
V
O(xVCC)
– 0.3 to 6 V
V
O
Output voltage
V
O(xVPP)
– 0.3 to 14 V
Continuous total power dissipation See Dissipation Rating Table
I
O(xVCC)
Internally Limited
I
O
Output current
I
O(xVPP)
Internally Limited
T
J
Operating virtual junction temperature range – 40 to 100 ° C
T
stg
Storage temperature range – 55 to 150 ° C
OC sink current 10 mA
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Not applicable for TPS2223A
T
A
≤ 25 ° C DERATING FACTOR T
A
= 70 ° C T
A
= 85 ° C
PACKAGE
(1)
POWER RATING ABOVE T
A
= 25 ° C POWER RATING POWER RATING
24 890 mW 8.9 mW/ ° C 489 mW 356 mW
DB
30 1095 mW 10.95 mW/ ° C 602 mW 438 mW
PWP 24 3322 mW 33.22 mW/ ° C 1827 mW 1329 mW
(1) These devices are mounted on an JEDEC low-k board (2-oz. traces on surface).
MIN MAX UNIT
V
I(3.3V)
(1)
3 3.6
Input voltage, V
I(3.3V)
is required for all circuit
operations. 5V and 12V are only required for V
I(5V)
3 5.5 V
their respective functions.
V
I(12V)
(2)
7 13.5
I
O(xVCC)
at T
J
= 100 ° C 1 A
I
O
Output current
I
O(xVPP)
at T
J
= 100 ° C 100 mA
f
(clock)
Clock frequency 2.5 MHz
Data 200
Latch 250
t
w
Pulse duration ns
Clock 100
Reset 100
t
h
Data-to-clock hold time (see Figure 2 ) 100 ns
t
su
Data-to-clock setup time (see Figure 2 ) 100 ns
t
d(latch)
Latch delay time (see Figure 2 ) 100 ns
t
d(clock)
Clock delay time (see Figure 2 ) 250 ns
(1) It is understood that for V
I(3.3V)
< 3 V, voltages within the absolute maximum ratings applied to pin 5V or pin 12V do not damage the IC.
(2) Not applicable for TPS2223A
2 Submit Documentation Feedback Copyright © 2002 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A