Datasheet

 
 
SLVS333 − AUGUST 2001
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APPLICATION INFORMATION
power supply sequencing
DSPs typically do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time if the other
supply is below the proper operating voltage.
system level design consideration
System level design considerations, such as bus contention, may require supply sequencing to be
implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered
down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the
output buffers are powered up, thus, preventing bus contention with other chips on the board.
power supply design consideration
For some DSP systems, the core supply may be required to provide a considerable amount of current until the
I/O supply is powered up. This extra current condition is a result of uninitialized logic within the DSP(s).
Decreasing the amount of time between the core supply power up and the I/O supply power up can minimize
the effects of this current draw.