Datasheet

 
 
SLVS399A − JANUARY 2002 − REVISED MAY 2006
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APPLICATION INFORMATION
DSP applications
Figure 28 shows the TPS2150 in a DSP application. DSPs use 1.8-V core voltage and 3.3-V I/O voltage. In this
type of application the TPS2150 adjustable LDO is configured for a 1.8-V output specifically for the DSP core
voltage.
The additional 3.3-V circuitry is powered through the switch of the TPS2150 only after the DSP is up and running.
LDO
LDO_PLDN
LDO_OUT
ADJ
LDO_IN
LDO_EN
SW_OUT
SW_PLDN
SW_PG
Switch
3.3 V
Power
Supply
TPS2150
SW_IN
Additional
3.3 V
Circuitry
0.1 µF
1.8 V
10 µF
0.1 µF
LDO_PG
SW_EN
3.3 V
4.7 µF
CVDD
DVDD
RESET
TMS320Cxxxx
0.1 µF
†
C can be very high-value capacitance
C
†
Figure 28. DSP Power Sequencing Application
system level design consideration of DSP power application
System level design considerations, such as bus contention, may require supply sequencing to be
implemented. In this case, the core supply should be powered up at the same time as (or prior to and powered
down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the
output buffers are powered up, thus preventing bus contention with other chips on the board.
For some DSP systems, the core supply may be required to provide a considerable amount of current until the
I/O supply is powered up. This extra current condition is a result of uninitialized logic within the DSP(s).
Decreasing the amount of time between the core supply power up and the I/O supply power up can minimize
the effects of this current draw.