Datasheet
SLVS399A − JANUARY 2002 − REVISED MAY 2006
18
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APPLICATION INFORMATION
external capacitor requirements on power lines
Ceramic bypass capacitors (0.01 µF to 0.1 µF) between SW_IN and GND and LDO_IN and GND, close to the
device, are recommended to improve load transient response and noise rejection. Bulk capacitors (4.7 µF or
higher) between SW_IN and GND and LDO_IN and GND are also recommended, especially if load transients
in the hundreds of milliamps with fast rise times are anticipated. A 66-µF bulk capacitor is recommended from
SW_OUT to ground, especially when the output load is heavy. This precaution helps reduce transients seen
on the power rails. Additionally, bypassing the outputs with a 0.1-µF ceramic capacitor improves the immunity
of the device to short-circuit transients.
LDO output capacitor requirements
Stabilizing the internal control loop of the LDO requires an output capacitor connected between LDO_OUT and
GND. The minimum recommended capacitance is 4.7 µF with an ESR value between 200 mΩ and 8.5 Ω. Solid
tantalum electrolytic, aluminum electrolytic and multilayer ceramic capacitors are all suitable, provided they
meet the ESR requirements (see Figures 15, 16, and 17). The adjustable LDO (for output voltages lower than
3 V) requires a bypass capacitor across the feedback resistor as shown in Figure 26. The nominal value of this
capacitor is determined by using the following equation:
C
f
+
1
ǒ
63.7 10
3
2 3.14 R1
Ǔ
* 4pF
where R1 is derived by programming the adjustable LDO (see programming the adjustable LDO regulator
section shown below).
R1
R2
C
f
0.1 µF 10 µF
LDO_OUT
ADJ
LDO_IN
LDO_EN
GND
4.7 µF
0.1 µF
TPS2140/41/50/51
Figure 26. LDO External Resistor Divider
programming the adjustable LDO regulator
The output voltage of the TPS2140/41/50/51 adjustable regulator is programmed using an external resistor
divider as shown in Figure 26. The output voltage is calculated using equation 2:
LDO_OUT + V
ref
ǒ
1 )
R1
R2
Ǔ
where V
ref
= 0.8 V typical (internal reference voltage).
Resistors R1 and R2 should be chosen for approximately 4-µA (minimum) divider current. Lower value resistors
can be used but offer no inherent advantage and waste more power. Higher values should be avoided as a
minimum load is required to sink the LDO forward leakage and maintain regulation. The recommended design
procedure is to choose R2 = 200 kΩ to set the divider current at 4-µA and then solve the LDO_OUT equation
for R1.
(1)
(2)