Datasheet

IN1
OUT
IN2
GND
8
7
6
5
STAT
D0
D1
ILIM
1
2
3
4
GND
STAT
D0
D1
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2114A
TPS2115A
SBVS044F –MARCH 2004–REVISED MAY 2012 www.ti.com
Table 1. Truth Table
D1 D0 V
I(IN2)
> V
I(IN1)
STAT OUT
(1)
0 0 X
(2)
Hi-Z IN2
0 1 No 0 IN1
0 1 Yes Hi-Z IN2
1 0 X 0 IN1
1 1 X 0 Hi-Z
(1) The under-voltage lockout circuit causes the output OUT to go Hi-Z if the selected power supply does not exceed the IN1/IN2 UVLO, or
if neither of the supplies exceeds the internal V
DD
UVLO.
(2) X = Don’t care.
PIN CONFIGURATIONS
PW PACKAGE
DRB PACKAGE
TSSOP-8
3mm × 3mm SON-8
(TOP VIEW)
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
NAME NO. I/O DESCRIPTION
TTL- and CMOS-compatible input pins. Each pin has a 1-μA pull-up. Table 1 illustrates the
D0 2 I
functionality of D0 and D1.
TTL- and CMOS-compatible input pins. Each pin has a 1-μA pull-up. Table 1 illustrates the
D1 3 I
functionality of D0 and D1.
GND 5 I Ground
Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above
IN1 8 I
the UVLO threshold and at least one supply exceeds the internal V
DD
UVLO.
Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is
IN2 6 I
above the UVLO threshold and at least one supply exceeds the internal V
DD
UVLO.
A resistor R
ILIM
from ILIM to GND sets the current limit I
L
to 250/R
ILIM
and 500/R
ILIM
for the
ILIM 4 I
TPS2114A and TPS2115A, respectively.
OUT 7 O Power switch output
STAT is an open-drain output that is Hi-Z if the IN2 switch is ON. STAT pulls low if the IN1
STAT 1 O
switch is ON or if OUT is Hi-Z (i.e., EN is equal to logic 0).
PAD — I Tie to GND. Connect to internal planes for improved heatsinking with multiple vias.
6 Copyright © 2004–2012, Texas Instruments Incorporated