Datasheet

IN1
IN2
OUT
GND
6
7
8
5
4
STAT
EN
VSNS
ILIM
GND
1
2
3
STAT
EN
VSNS
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2112A
TPS2113A
www.ti.com SBVS045C –MARCH 2004–REVISED MAY 2012
DEVICE INFORMATION
TRUTH TABLE
EN V
I(VSNS)
> 0.8 V
(1)
V
I(IN2)
> V
I(IN1)
STAT OUT
(2)
0 Yes X 0 IN1
0 No No 0 IN1
0 No Yes Hi-Z IN2
1 X X 0 Hi-Z
(1) X = Don’t care.
(2) The undervoltage lockout circuit causes the output (OUT) to go Hi-Z if the selected power supply does not exceed the IN1/IN2 UVLO, or
if neither of the supplies exceeds the internal V
DD
UVLO.
PIN CONFIGURATIONS
PW PACKAGE
DRB PACKAGE
TSSOP-8
SON-8
(TOP VIEW)
(TOP VIEW)
Table 1. TERMINAL FUNCTIONS
TERMINAL
NAME NO. I/O DESCRIPTION
TTL- and CMOS-compatible input with a 1-μA pull-up. The Truth Table illustrates the
EN 2 I
functionality of EN.
GND 5 Power Ground
Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above
IN1 8 I
the UVLO threshold and at least one supply exceeds the internal V
DD
UVLO.
Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is
IN2 6 I
above the UVLO threshold and at least one supply exceeds the internal V
DD
UVLO.
A resistor (R
ILIM
) from ILIM to GND sets the current limit (I
L
) to 250/R
ILIM
and 500/R
ILIM
for
ILIM 4 I
the TPS2112A and TPS2113A, respectively.
OUT 7 O Power switch output
STAT is an open-drain output that is Hi-Z if the IN2 switch is ON. STAT pulls low if the IN1
STAT 1 O
switch is ON or if OUT is Hi-Z (that is, EN is equal to logic '0')
An internal power FET connects OUT to IN1 if the VSNS voltage is greater than 0.8 V.
VSNS 3 I Otherwise, the FET connects OUT to the higher of IN1 and IN2. The Truth Table illustrates
the functionality of VSNS.
DRB package only. Connect to GND. Must be connected to large copper area in order to
Pad — Power
meet stated package dissipation ratings.
Copyright © 2004–2012, Texas Instruments Incorporated 7